Abstract: A method for auto enlarging bend portion width and a computer readable recording medium for storing program thereof are provided. The method can enlarge the bend portion width from an original width to an intended width in layout. Wherein, the terminals of the center line of the bend is a first turn point and a second turn point, respectively. The method includes following steps. First calculating the original width, the intended width, the coordinates of the first turn point and the second turn point to obtain a plurality coordinates of the corner-points of the polygon. Wherein, the width of the polygon is the intended width. Then add the polygon into the original layout.

Abstract: A method for placing probing pad and a computer readable recording medium for storing a program thereof are provided. The method is suitable for placing the probing pads in an integrated circuit (IC). Wherein, appropriate grid spacing is determined and a plurality of grids with fixed grid spacing is generated. The location of each preformed grid on the net connecting to the interesting pin is defined as first candidate probing points. Then, based on the metal layer where the first candidate probing points are located and the corresponding locations between the first candidate probing points and the interesting pin, one candidate probing point among all of the first candidate probing points on each net where the probing pad can be placed on is selected as the probing point. Finally, a probing pad is placed on each of the selected probing points.

Abstract: A method for auto enlarging bend portion width and a computer readable recording medium for storing program thereof are provided. The method can enlarge the bend portion width from an original width to an intended width in layout. Wherein, the terminals of the center line of the bend is a first turn point and a second turn point, respectively. The method includes following steps. First calculating the original width, the intended width, the coordinates of the first turn point and the second turn point to obtain a plurality coordinates of the corner-points of the polygon. Wherein, the width of the polygon is the intended width. Then add the polygon into the original layout.

Abstract: A method for placing probing pad and a computer readable recording medium for storing a program thereof are provided. The method is suitable for placing the probing pads in an integrated circuit (IC). Wherein, appropriate grid spacing is determined and a plurality of grids with fixed grid spacing is generated. The location of each preformed grid on the net connecting to the interesting pin is defined as first candidate probing points. Then, based on the metal layer where the first candidate probing points are located and the corresponding locations between the first candidate probing points and the interesting pin, one candidate probing point among all of the first candidate probing points on each net where the probing pad can be placed on is selected as the probing point. Finally, a probing pad is placed on each of the selected probing points.

Abstract: A method is capable of generating a command file of a group of design rule check (DRC) rules or layout versus schematic (LVS) rules and layout parasitic extraction (LPE) rules that can be used by a layout verification tool to verify the layout and the parasitic characteristics of an integrated circuit. The method comprises choosing whether to generate a command file of DRC rules or a command file of LVS/LPE rules, selecting a process from a group of processes, setting a set of parameters, and extracting program codes from a plurality of modules according to the selected process and the set of parameters so as to generate a command file of DRC rules or LVS/LPE rules.

Abstract: A method is capable of generating a command file of a group of design rule check (DRC) rules or layout versus schematic (LVS) rules and layout parasitic extraction (LPE) rules that can be used by a layout verification tool to verify the layout and the parasitic characteristics of an integrated circuit. The method comprises choosing whether to generate a command file of DRC rules or a command file of LVS/LPE rules, selecting a process from a group of processes, setting a set of parameters, and extracting program codes from a plurality of modules according to the selected process and the set of parameters so as to generate a command file of DRC rules or LVS/LPE rules.

Abstract: A mesh capacitor structure in an integrated circuit can be made up by arranging at least a unit capacitor module in a coupling way, thereby enhancing its total capacitance by coupling capacitance. The unit capacitor module includes a plurality of first conductive strips extending in parallel with each other in a lateral direction and a plurality of second conductive strips formed over the plurality of first conductive strips and extending in parallel with each other in a longitudinal direction. In addition, a plurality of conductive plugs are formed at intersections between the odd-numbered second conductive strips and the odd-numbered or even-numbered first conductive strips, thereby forming a first electrode, and between the even-numbered second conductive strips and the even-numbered or odd-numbered first conductive strips, thereby forming a second electrode with an electrical polarity opposite to that of the first electrode.