Abstract: Method and apparatus for efficiently analyzing visual defects of an integrated circuit wafer in the manufacturing process thereof by utilizing an asymmetric visual defect review methodology that can effectively extract high yield-killing defects out of numerous reported defects within the limited capacity and manpower available for review. Roughly described, the method comprises inspecting the semiconductor wafer, thereby obtaining the defect location and defect size, sampling the defects asymmetrically by determining asymmetrical defect review ratios, and thereby reviewing the defects asymmetrically. Also described is a method of asymmetrically sampling visual defects that can effectively extract out high yield-killing defects from a mass of defects by determining asymmetric defect review ratios, and a system for use in sampling visual defects asymmetrically.

Abstract: Method and apparatus for efficiently analyzing visual defects of an integrated circuit wafer in the manufacturing process thereof by utilizing an asymmetric visual defect review methodology that can effectively extract high yield-killing defects out of numerous reported defects within the limited capacity and manpower available for review. Roughly described, the method comprises inspecting the semiconductor wafer, thereby obtaining the defect location and defect size, sampling the defects asymmetrically by determining asymmetrical defect review ratios, and thereby reviewing the defects asymmetrically. Also described is a method of asymmetrically sampling visual defects that can effectively extract out high yield-killing defects from a mass of defects by determining asymmetric defect review ratios, and a system for use in sampling visual defects asymmetrically.

Abstract: A method of boosting wafer-cleaning efficiency and increasing process yield. Different types of process particles are deposited on a test wafer. The test wafer is cleaned in a cleaning operation. The test wafer is scanned to determine the types of process particles that are completely removed and the types of process particles that remain over the test wafer. The results of wafer scanning are used to provide an assessment of the efficiency of the cleaning operation. Operation parameters of the cleaning operation are adjusted to maximize the wafer-cleaning efficiency.

Abstract: A method of preventing the corrosion of tungsten plug within a substrate in the process of manufacturing a semiconductor device. The tungsten plug within the substrate is coupled to a conductive line on the substrate. The process includes treating the substrate with a charge neutralizer so that charges accumulated on the surface of the conductive line during etching is removed and conducting a wet-cleaning operation thereafter.

Abstract: A method of fabricating a shallow trench isolation. A wafer on which a mask layer is formed is provided. A blank wafer is provided and disposed in an etching machine to perform an etching process. Whether the blank wafer contains a defect is inspected. If the number of defects occurring on the blank wafer is within an acceptable quantity, the wafer is disposed in the etching machine for performing an etching process and defining a trench. The trench is then filled with an insulation layer. The mask layer is removed to form a shallow trench isolation.

Abstract: A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.

Abstract: A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.

Abstract: A method of boosting wafer-cleaning efficiency and increasing process yield. Different types of process particles are deposited on a test wafer. The test wafer is cleaned in a cleaning operation. The test wafer is scanned to determine the types of process particles that are completely removed and the types of process particles that remain over the test wafer. The results of wafer scanning are used to provide an assessment of the efficiency of the cleaning operation. Operation parameters of the cleaning operation are adjusted to maximize the wafer-cleaning efficiency.