Patents by Inventor Szu Wang

Szu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990429
    Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Kung-Chen Yeh, Li-Chung Kuo, Pu Wang, Szu-Wei Lu
  • Patent number: 11923259
    Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Tsung-Fu Tsai
  • Publication number: 20230140671
    Abstract: A socket connector device for mating with a central processing unit having conductive portions is provided. The socket connector device includes a circuit module, a terminal module, and a cover plate. The terminal module is placed on the circuit module. The terminal module includes a terminal block. The terminal module includes a terminal block, multiple rows of terminals integrally formed with the terminal block, and a support housing protecting the terminal block. Each terminal includes a first contact end and a second contact end corresponding to each other. The second contact end protrudes from the support housing. Each first contact end electrically contacts one conductive portion, and each second contact end electrically contacts the circuit module. The cover plate is rotatably assembled on the terminal module, so that the conductive portions of the central processing unit electrically contact or do not contact the terminals of the terminal block.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 4, 2023
    Applicants: SUYIN OPTRONICS CORP.
    Inventor: Jih-szu WANG
  • Publication number: 20230138545
    Abstract: The present invention provides a test connector device for testing a component to be tested having conductive portions. The test connector device includes a base, a terminal block, and a limiting member. The terminal block is disposed on the base. The terminal block includes a substrate and terminals arranged in multiple rows and formed in an integral form with the substrate. Each of the terminals includes a first contact end and a second contact end corresponding to each other. The component to be tested is placed on the limiting member and movably assembled to one side of the base. The limiting member includes a positioning assembly and limiting slots where the first contact ends protrude out. The positioning assembly is movably fastened to the base, so that the first contact ends contact the conductive portions. Accordingly, the present invention enhances reliability, stability, and transmission efficiency during tests.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 4, 2023
    Applicants: Suyin Optronics Corp.
    Inventor: Jih-szu WANG
  • Publication number: 20070268753
    Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.
    Type: Application
    Filed: July 30, 2007
    Publication date: November 22, 2007
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Szu Wang
  • Publication number: 20070217176
    Abstract: A handheld communication apparatus includes a metallic insert molding member, a circuit board and a shielding frame. The metallic insert molding member includes a metal plate. An electronic component is mounted on the circuit board. The shielding frame defines opposite first and second openings, wherein the shielding frame is bonded to the metal plate of the metallic insert molding member at the first opening, thereby forming a shielding case. The electronic component on the circuit board is inserted into the second opening of the shielding frame to be shielded by the shielding case.
    Type: Application
    Filed: May 31, 2006
    Publication date: September 20, 2007
    Applicant: ARIMA COMMUNICATIONS CORPORATION
    Inventor: Szu Wang
  • Publication number: 20060202252
    Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.
    Type: Application
    Filed: January 3, 2006
    Publication date: September 14, 2006
    Inventors: Szu Wang, Hang-Ting Lue
  • Patent number: D483079
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: December 2, 2003
    Inventors: Po Szu Wang, Josephine M. Yang