Patents by Inventor Szu-Wei Chang
Szu-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128157Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.Type: ApplicationFiled: July 25, 2022Publication date: April 18, 2024Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
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Patent number: 11948930Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.Type: GrantFiled: November 13, 2020Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
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Patent number: 11946300Abstract: A lever-operated latch device includes an assembly of a case body, an actuation body mounted on the case body, a linking member and a slide body. The actuation body has a free end and a pivoted end pivotally connected with the case body in cooperation with elastic members. The free end of the actuation body is formed with two protruding arms and an opening section positioned between the protruding arms. An operation section is disposed in the opening section. The linking member has a first end pivotally connected with the free end of the actuation body (or the operation section) and a second end connected with the slide body. When an operator presses the operation section, the actuation body is permitted to move from a closed position to an opened position so as to drive the linking member and the slide body to move.Type: GrantFiled: November 3, 2021Date of Patent: April 2, 2024Assignee: Fositek CorporationInventors: An Szu Hsu, Chun Han Lin, Che Wei Chang
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Publication number: 20240105629Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
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Publication number: 20240087964Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
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Patent number: 11929261Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.Type: GrantFiled: November 13, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Szu-Wei Lu, Chen-Hua Yu
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Patent number: 11922887Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.Type: GrantFiled: July 6, 2021Date of Patent: March 5, 2024Assignee: Apple Inc.Inventors: Shinya Ono, Chin-Wei Lin, Chuan-Jung Lin, Gihoon Choo, Hassan Edrees, Hei Kam, Jung Yen Huang, Pei-En Chang, Rungrot Kitsomboonloha, Szu-Hsien Lee, Zino Lee
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Patent number: 10965306Abstract: A successive approximation register analog-to-digital converter includes a comparator circuit, a capacitor group, an additional capacitor and a control circuit. The comparator circuit compares voltages at first and second input terminals thereof to generate a comparison result. The capacitor group and the additional capacitor are coupled to the first input terminal. The control circuit controls voltages of capacitors of the capacitor group according to the comparison result. In a first period, the control circuit provides a first voltage to the first input terminal and the additional capacitor, and provides an analog signal to the capacitors. In a second period, the control circuit stops providing the first voltage and controls a specific capacitor of the capacitor group to enter into a floating state. In a third period, the control circuit provides a second voltage to the additional capacitor. The second voltage is lower than the first voltage.Type: GrantFiled: August 28, 2019Date of Patent: March 30, 2021Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Che-Hao Chiang, Szu-Wei Chang
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Patent number: 10790846Abstract: A successive approximation register analog-to-digital converter including a first capacitor group, a second capacitor group and a control circuit is provided. Each of the first and second capacitor groups includes a plurality of capacitors coupled to a common node. In a sampling mode, the control circuit provides an analog signal to the first capacitor group and provides a first voltage to the common node and the second capacitor group. In a sampling mode, the control circuit stops providing the first voltage to the common node and provides a second voltage to the second capacitor group. In a data converting mode, the control circuit reads voltage values of the capacitors of the first capacitor group in sequence. Each when the voltage of at least one specific capacitor in the first capacitor group is read, one capacitor of the second capacitor group is electrically floated.Type: GrantFiled: August 6, 2019Date of Patent: September 29, 2020Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Szu-Wei Chang, Che-Hao Chiang, Tu-Hsiu Wang
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Publication number: 20200106454Abstract: A successive approximation register analog-to-digital converter including a first capacitor group, a second capacitor group and a control circuit is provided. Each of the first and second capacitor groups includes a plurality of capacitors coupled to a common node. In a sampling mode, the control circuit provides an analog signal to the first capacitor group and provides a first voltage to the common node and the second capacitor group. In a sampling mode, the control circuit stops providing the first voltage to the common node and provides a second voltage to the second capacitor group. In a data converting mode, the control circuit reads voltage values of the capacitors of the first capacitor group in sequence. Each when the voltage of at least one specific capacitor in the first capacitor group is read, one capacitor of the second capacitor group is electrically floated.Type: ApplicationFiled: August 6, 2019Publication date: April 2, 2020Inventors: Szu-Wei CHANG, Che-Hao CHIANG, Tu-Hsiu WANG
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Publication number: 20200076444Abstract: A successive approximation register analog-to-digital converter includes a comparator circuit, a capacitor group, an additional capacitor and a control circuit. The comparator circuit compares voltages at first and second input terminals thereof to generate a comparison result. The capacitor group and the additional capacitor are coupled to the first input terminal. The control circuit controls voltages of capacitors of the capacitor group according to the comparison result. In a first period, the control circuit provides a first voltage to the first input terminal and the additional capacitor, and provides an analog signal to the capacitors. In a second period, the control circuit stops providing the first voltage and controls a specific capacitor of the capacitor group to enter into a floating state. In a third period, the control circuit provides a second voltage to the additional capacitor. The second voltage is lower than the first voltage.Type: ApplicationFiled: August 28, 2019Publication date: March 5, 2020Inventors: Che-Hao CHIANG, Szu-Wei CHANG
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Patent number: 10511318Abstract: A digital background calibration circuit including a digital random number generator, an analog-to-digital converter (ADC) and a plurality of switches is provided. The digital random number generator is configured to generate a first digital sequence having a plurality of bits. The ADC includes a plurality of sampling capacitors. The switches receive the first digital sequence and are coupled to the sampling capacitors. During a calibration period, the digital random number generator controls the sampling capacitors via the switches to sample the first digital sequence.Type: GrantFiled: October 31, 2018Date of Patent: December 17, 2019Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Che-Hao Chiang, Szu-Wei Chang, Wei-Chan Hsu, Tu-Hsiu Wang
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Publication number: 20190253063Abstract: A digital background calibration circuit including a digital random number generator, an analog-to-digital converter (ADC) and a plurality of switches is provided. The digital random number generator is configured to generate a first digital sequence having a plurality of bits. The ADC includes a plurality of sampling capacitors. The switches receive the first digital sequence and are coupled to the sampling capacitors. During a calibration period, the digital random number generator controls the sampling capacitors via the switches to sample the first digital sequence.Type: ApplicationFiled: October 31, 2018Publication date: August 15, 2019Inventors: Che-Hao CHIANG, Szu-Wei CHANG, Wei-Chan HSU, Tu-Hsiu WANG
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Publication number: 20140127704Abstract: The present invention provides a kit for diagnosing the cardiomyopathy comprising an antibody or oligonucleotide for measuring an expression level of nuclear receptor interaction protein (NRIP). The present invention also provides a method of predicting a risk of cardiomyopathy for a subject. The present invention further provides a method of screening an agent for treating cardiomyopathy.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicant: NATIONAL TAIWAN UNIVERSITYInventors: Show-Li CHEN, Ssu-Yu LIN, Szu-Wei CHANG, Hsin-Hsiung CHEN
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Publication number: 20120065122Abstract: The present invention directed to a method for modulating the expression level of slow myosin comprising administering to a subject in need thereof a therapeutically effective amount of nuclear receptor interaction protein (NRIP) modulator and calmodulin, and a pharmaceutically acceptable carrier.Type: ApplicationFiled: September 15, 2010Publication date: March 15, 2012Applicant: NATIONAL TAIWAN UNIVERSITYInventors: Show-Li Chen, Hsin-Hsiung Chen, Szu-Wei Chang, Jim Pan, Kuan-Liang Lin
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Publication number: 20120021998Abstract: The present invention relates to a method for treating a subject suffering from growth of AR-containing tumor cells, comprising administrating the subject an effective amount of DDB2. The present invention also relates to a kit for the diagnosis of cancer.Type: ApplicationFiled: July 20, 2010Publication date: January 26, 2012Applicant: NATIONAL TAIWAN UNIVERSITYInventors: Show-Li Chen, Hsuan-Hao Chen, Kuan-Liang Lin, Hsin-Hsiung Chen, Szu-Wei Chang