Patents by Inventor Szu-Wei Chen
Szu-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071982Abstract: In an embodiment, a device bonding apparatus is provided. The device bonding apparatus includes a first process station configured to receive a wafer; a first bond head configured to carry a die to the wafer, wherein the first bonding head includes a first rigid body and a vacuum channel in the first rigid body for providing an attaching force for carrying the die to the wafer; and a second bond head configured to press the die against the wafer, the second bond head including a second rigid body and an elastic head disposed over the second rigid body for pressing the die, the elastic head having a center portion and an edge portion surrounding the center portion, the center portion of the elastic head having a first thickness, the edge portion of the elastic head having a second thickness, the second thickness being greater than the second thickness.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
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Publication number: 20240071849Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
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Patent number: 11726709Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.Type: GrantFiled: August 17, 2020Date of Patent: August 15, 2023Assignee: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yu-Siang Yang, Szu-Wei Chen, Wei Lin
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Publication number: 20230037782Abstract: A method for training an asymmetric generative adversarial network to generate an image and an electronic apparatus using the same are provided. The method includes the following. A first real image belonging to a first category, a second real image belonging to a second category and a third real image belonging to a third category are input to an asymmetric generative adversarial network for training the asymmetric generative adversarial network, and the asymmetric generative adversarial network includes a first generator, a second generator, a first discriminator and a second discriminator. A fourth real image belonging to the second category is input to the first generator in the trained asymmetric generative adversarial network to generate a defect image.Type: ApplicationFiled: August 29, 2021Publication date: February 9, 2023Applicant: PHISON ELECTRONICS CORP.Inventors: Yi-Hsiang MA, Szu-Wei Chen, Yu-Hung Lin, An-Cheng Liu
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Publication number: 20220027089Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.Type: ApplicationFiled: August 17, 2020Publication date: January 27, 2022Applicant: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yu-Siang Yang, Szu-Wei Chen, Wei Lin
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Patent number: 10984870Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.Type: GrantFiled: March 5, 2019Date of Patent: April 20, 2021Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
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Patent number: 10978163Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.Type: GrantFiled: October 14, 2019Date of Patent: April 13, 2021Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
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Publication number: 20210082522Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.Type: ApplicationFiled: October 14, 2019Publication date: March 18, 2021Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
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Patent number: 10892026Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.Type: GrantFiled: June 8, 2018Date of Patent: January 12, 2021Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
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Patent number: 10872667Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; determining whether a first ratio of a first quantity of a first bit value and a second quantity of a second bit value in the first data is greater than a threshold; when the first ratio is not greater than the threshold, performing a decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold, not performing the decoding operation according to the first data.Type: GrantFiled: January 16, 2019Date of Patent: December 22, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
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Patent number: 10776053Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.Type: GrantFiled: January 28, 2019Date of Patent: September 15, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
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Publication number: 20200227120Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.Type: ApplicationFiled: March 5, 2019Publication date: July 16, 2020Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
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Publication number: 20200183623Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.Type: ApplicationFiled: January 28, 2019Publication date: June 11, 2020Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
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Publication number: 20200185032Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; determining whether a first ratio of a first quantity of a first bit value and a second quantity of a second bit value in the first data is greater than a threshold; when the first ratio is not greater than the threshold, performing a decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold, not performing the decoding operation according to the first data.Type: ApplicationFiled: January 16, 2019Publication date: June 11, 2020Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
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Patent number: 10679707Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.Type: GrantFiled: September 3, 2018Date of Patent: June 9, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Tsai-Hao Kuo, Szu-Wei Chen, Lih Yuarn Ou, Hsiao-Yi Lin
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Patent number: 10622077Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.Type: GrantFiled: August 31, 2017Date of Patent: April 14, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang
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Patent number: 10586596Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units and a memory control circuit unit and a memory storage apparatus using the same are provided. Each of the physical erasing units has a plurality of physical programming unit sets, and each of the physical programming unit sets has a plurality of physical programming unit. The method includes receiving data and arranging the data to generate a first data stream and a second data stream. The method also includes encoding the first data stream and the second data stream to generate a third data stream, and issuing a programming command sequence to write the first data stream, the second data stream and the third data stream respectively into a first physical programming unit, a second physical programming unit and a third physical programming unit of a physical programming unit set.Type: GrantFiled: January 23, 2017Date of Patent: March 10, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
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Publication number: 20200035306Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.Type: ApplicationFiled: September 3, 2018Publication date: January 30, 2020Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Tsai-Hao Kuo, Szu-Wei Chen, Lih Yuarn Ou, Hsiao-Yi Lin
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Publication number: 20190318791Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.Type: ApplicationFiled: June 8, 2018Publication date: October 17, 2019Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, An-Cheng Liu, Szu-Wei Chen, Yu-Siang Yang
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Patent number: D1024051Type: GrantFiled: August 10, 2021Date of Patent: April 23, 2024Assignee: Acer IncorporatedInventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng