Patents by Inventor Szu-Yao Yu

Szu-Yao Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128324
    Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
  • Patent number: 11424408
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 23, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20220238632
    Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Inventors: Kuo-Chih Lai, Chi-Mao Hsu, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Hsin-Fu Huang
  • Publication number: 20210351347
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Patent number: 11165019
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20210057643
    Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.
    Type: Application
    Filed: September 20, 2019
    Publication date: February 25, 2021
    Inventors: Shih-Min Chou, Kuo-Chih Lai, Wei-Ming Hsiao, Hui-Ting Lin, Szu-Yao Yu, Nien-Ting Ho, Hsin-Fu Huang, Chin-Fu Lin