Patents by Inventor Szu-Ying Chen

Szu-Ying Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120209
    Abstract: The problem of forming a deep trench isolation structure suitable for photodetectors with small pitch is solved by a process in which a grid of trenches is etched from the front side using high energy plasma followed by annealing. The trenches are filled with an oxide followed by etching to recess the oxide. The trench recesses are filled with semiconductor to form a grid-shaped semiconductor structure. After FEOL processing, BEOL processing, attachment to a second substrate, and thinning from the back side, an etch removes the oxide from the back side. The etch stops on the grid-shaped semiconductor structure. The trenches are then lined and filled from the back side. The front side etch allows the trenches to be made narrow and with highly vertical sidewalls. Lining and filling the trenches from the back side provides good optical and electrical isolation.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Inventors: Shu-Ting Tsai, Tzu-Jui Wang, U-Ting Chen, Shyh-Fann Ting, Szu-Ying Chen
  • Publication number: 20250101342
    Abstract: The present invention is for an acidic cleaning composition which has excellent cleaning performance, low toxicity and good antimicrobial efficacy. The inventive acidic cleaning compositions are capable of sanitizing or disinfecting a variety of hard surfaces. The inventive acidic cleaning compositions can take a variety of forms, such as: disinfecting wipes, all-purpose disinfecting sprays, kitchen cleaners, bathroom cleaners, toilet cleaners, etc. The inventive acidic cleaning compositions have good cleaning properties and low residue.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Nancy A. FALK, David R. SCHEUING, Heather L. DAY, Szu-Ying CHEN, Bryan K. PARRISH, Fanny FRAUSTO, Eric G. GHARAKHANIAN, William KING
  • Publication number: 20250098259
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes forming a first fin structure and a second fin structure from a substrate, depositing a first conformal layer over the first and second fin structures and between the first and second fin structures, depositing a second conformal layer on the first conformal layer, depositing a third conformal layer on the second conformal layer, depositing a fourth conformal layer on the third conformal layer, depositing a first insulating material on the fourth conformal layer between the first and second fin structures, and depositing a second insulating material on the first insulating material. The first and second fin structures are embedded by the second insulating material. The method further includes removing portions of the second insulating material and the first, second, third, and fourth conformal layers to expose the first and second fin structures.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 20, 2025
    Inventors: Ya-Wen CHIU, Yi-Hua CHENG, Szu-Ying CHEN, Zheng-Yang PAN
  • Publication number: 20250079162
    Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Inventors: Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Yi Che Chan, Chih Ping Liao, YungHao Wang, Sen-Hong Syue
  • Publication number: 20250056870
    Abstract: Embodiments of the present disclosure provide a method for selectively forming a seed layer over semiconductor fins. Some embodiments provide forming the selective seed layer using a mono-silane at an increased temperature. Some embodiments provide depositing a hetero-crystalline silicon cap layer over the bottom-up gap layer to improve gap filling and tune profiles of fin structures.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: Ya-Wen Chiu, De Jhong Liao, Yu-Yu Chen, Szu-Ying Chen, Zheng-Yang Pan
  • Patent number: 12206012
    Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Szu-Ying Chen
  • Patent number: 12203051
    Abstract: The present invention is for an acidic cleaning composition which has excellent cleaning performance, low toxicity and good antimicrobial efficacy. The inventive acidic cleaning compositions are capable of sanitizing or disinfecting a variety of hard surfaces. The inventive acidic cleaning compositions can take a variety of forms, such as: disinfecting wipes, all-purpose disinfecting sprays, kitchen cleaners, bathroom cleaners, toilet cleaners, etc. The inventive acidic cleaning compositions have good cleaning properties and low residue.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: January 21, 2025
    Assignee: THE CLOROX COMPANY
    Inventors: Nancy A. Falk, David R. Scheuing, Heather L. Day, Szu-Ying Chen, Bryan K. Parrish, Fanny Frausto, Eric G. Gharakhanian, William King
  • Patent number: 12183573
    Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Yi Che Chan, Chih Ping Liao, YungHao Wang, Sen-Hong Syue
  • Publication number: 20240405096
    Abstract: A method includes etching a first trench in a semiconductor substrate to form a first fin and a second fin, and forming a shallow trench isolation (STI) region in the first trench, where forming the STI region includes depositing a first dielectric layer over top surfaces of the first fin and the second fin, and on sidewalls and a bottom surface of the first trench, the first dielectric layer including carbon, depositing a second dielectric layer over the first dielectric layer, and in the first trench, where the second dielectric layer fills the first trench, and performing an anneal process, where the anneal process releases carbon from the first dielectric layer into the second dielectric layer.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Yun Chen Teng, Szu-Ying Chen, Yung-Chung Chen, Sen-Hong Syue, Chi On Chui
  • Patent number: 12148781
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a gate stack over a front surface of a substrate. A mask layer is formed over at least a portion of the gate stack and a portion of the front surface. A plurality of dopants are implanted into one or more regions of the substrate that are not covered by the mask layer to form one or more doped isolation features in the substrate. The one or more doped isolation features are formed to have a convex portion at least partially under the gate stack.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Min-Feng Kao, Jen-Cheng Liu, Feng-Chi Hung, Dun-Nian Yaung
  • Publication number: 20240376441
    Abstract: Provided herein are compositions and methods for driving high expression of a transgene. Compositions and methods for driving high expression of a transgene comprising one or more human-derived regulatory elements, which, when operably linked to a transgene, can result in high expression of the transgene in one or more cell types or tissues.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 14, 2024
    Inventors: Kartik RAMAMOORTHI, Stephanie TAGLIATELA, Anne TANENHAUS, Andrew YOUNG, Szu-Ying CHEN, Chi ZHANG, Stephanie MARTIN, David OBERKOFLER
  • Publication number: 20240379461
    Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240363736
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Huicheng Chang, Chien-Tai Chan, Liang-Yin Chen, Yee-Chia Yeo, Szu-Ying Chen
  • Publication number: 20240355927
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an expansion film over a substrate. The substrate has a base portion, a first fin, and a second fin over the base portion. The method includes forming an isolation layer over the expansion film. The method includes annealing the expansion film, the substrate, and the isolation layer. The method includes partially removing the isolation layer and the expansion film to expose the first upper portion of the first fin and the second upper portion of the second fin. The method includes forming a gate stack wrapping around the first upper portion of the first fin and the second upper portion of the second fin.
    Type: Application
    Filed: April 24, 2023
    Publication date: October 24, 2024
    Inventors: Szu-Ying CHEN, Sen-Hong SYUE, Chi On CHUI
  • Patent number: 12104175
    Abstract: Provided herein are compositions and methods for driving high expression of a transgene. Compositions and methods for driving high expression of a transgene comprising one or more human-derived regulatory elements, which, when operably linked to a transgene, can result in high expression of the transgene in one or more cell types or tissues.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: October 1, 2024
    Assignee: Encoded Therapeutics, Inc.
    Inventors: Kartik Ramamoorthi, Stephanie Tagliatela, Anne Tanenhaus, Andrew Young, Szu-Ying Chen, Chi Zhang, Stephanie Martin, David Oberkofler
  • Patent number: 12087847
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Huicheng Chang, Chien-Tai Chan, Liang-Yin Chen, Yee-Chia Yeo, Szu-Ying Chen
  • Patent number: 12068287
    Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung
  • Publication number: 20240274606
    Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the fist insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 15, 2024
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240266229
    Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.
    Type: Application
    Filed: April 3, 2024
    Publication date: August 8, 2024
    Inventors: Szu-Ying Chen, Po-Kang Ho, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240266375
    Abstract: In some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. A FDTI trench is formed from a frontside of a substrate between a first pixel region and a second pixel region and then filled to form a FDTI structure. A cap layer is formed over the FDTI structure overlying the first pixel region and the second pixel region of the substrate. A first photodiode is formed in the first pixel region and a second photodiode is formed in the second pixel region. A FD node is formed within the cap layer between the first pixel region and the second pixel region overlying the FDTI structure. The FD node may be shared by a group of pixel regions not separated by the FDTI structure, such that few metal contacts are needed and thus reduce parasitic capacitance issues of proximity metal contacts.
    Type: Application
    Filed: May 9, 2023
    Publication date: August 8, 2024
    Inventors: Chao-Te Liu, Yen-Chen Lin, Szu-Ying Chen, Chen-Jong Wang, Dun-Nian Yaung