Abstract: The problem of forming a deep trench isolation (DTI) structure suitable for photodetectors having a narrow pitch is solved by a process in which a p-doped epitaxial layer is grown on the sidewalls of trenches formed by etching. The epitaxial layer becomes part of the active region of any adjacent photodetectors and narrows the DTI structure that is formed by dielectric in the trenches. The epitaxial layer may be allowed to close the trench mouths and to grow on the front side. Floating diffusion regions and the like may then be formed directly over the DTI structure. Optionally, dislocations in the epitaxial layer are removed by laser annealing. Optionally the epitaxial layer is planarized after annealing. The trenches may be accessed from the back side by thinning the substrate, whereupon the trenches may be partially or completely filled with dielectric to form the DTI structure.

Abstract: A semiconductor structure for a memory device is provided. The semiconductor structure includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer. The first layer is between the second layer and the first gate structure. The first layer and the second layer include a same semiconductor material and same dopants. The first layer has a first dopant concentration, and the second layer has a second dopant concentration. The second gate structure includes a p-type gate structure, and second dopant concentration of the second layer is greater than the first dopant concentration of the first layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an epitaxial layer arranged on a semiconductor body. A trap-rich layer is arranged on the epitaxial layer, a dielectric layer is arranged on the trap-rich layer, and an active semiconductor layer is arranged on the dielectric layer. A semiconductor material is arranged on the epitaxial layer and laterally beside the active semiconductor layer. The epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.

Abstract: A method for forming a semiconductor structure includes receiving a substrate including a first gate structure; forming a first semiconductor layer over the first gate structure, forming a second semiconductor layer on the first semiconductor layer, performing an etching back operation to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer with an etchant, the etching rate of the first semiconductor layer upon exposure to the etchant is greater than an etching rate of the second semiconductor layer upon exposure to the etchant; forming a hard mask spacer over the first semiconductor layer and the second semiconductor layer, a portion of the second semiconductor layer is exposed through the hard mask spacer; removing the portions of the second semiconductor layer and the first semiconductor layer through the hard mask spacer to form a second gate structure and expose a portion of the substrate.

Abstract: A semiconductor structure includes a capacitor structure and a contact structure. The capacitor structure includes an electrode layer, a protective dielectric layer, and a capacitor dielectric layer. The protective dielectric layer covers a top surface of the electrode layer. The capacitor dielectric layer is on the protective oxide layer. The contact structure penetrates the protective oxide layer and electrically connects to the electrode layer.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.

Abstract: A semiconductor structure for a memory device includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer, and the first layer is between the second layer and the first gate structure. The first layer and the second layer include a same semiconductor material and same dopants. The first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the firs dopant concentration.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Abstract: A method for forming a semiconductor structure includes receiving a substrate including a first gate structure; forming a first semiconductor layer over the first gate structure, forming a second semiconductor layer on the first semiconductor layer, performing an etching back operation to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer with an etchant, the etching rate of the first semiconductor layer upon exposure to the etchant is greater than an etching rate of the second semiconductor layer upon exposure to the etchant; forming a hard mask spacer over the first semiconductor layer and the second semiconductor layer, a portion of the second semiconductor layer is exposed through the hard mask spacer; removing the portions of the second semiconductor layer and the first semiconductor layer through the hard mask spacer to form a second gate structure and expose a portion of the substrate.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.

Abstract: A semiconductor structure for a memory device includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer, and the first layer is between the second layer and the first gate structure. The first layer and the second layer include a same semiconductor material and same dopants. The first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the firs dopant concentration.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.

Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.