Abstract: A semiconductor device includes a backside gate etch stop layer (ESL) on a backside of a first gate stack, wherein a plurality of first nanostructures overlaps the backside gate ESL. The backside gate ESL may comprise a high-k dielectric material. The semiconductor device further includes the plurality of first nanostructures extending between first source/drain regions and a plurality of second nanostructures over the plurality of first nanostructures and extending between second source/drain regions. A first gate stack is disposed around the plurality of first nanostructures, and a second gate stack over the first gate stack is disposed around the plurality of second nanostructures. A backside gate contact extends through the backside gate ESL to be electrically coupled to the first gate stack.

Abstract: An integrated circuit device includes a first-type transistor and a second-type transistor stacked with each other at a front side of a substrate. The second-type transistor is between the first-type transistor and the substrate. The integrated circuit device also includes a front-side inductor having one or more conductors in a front-side upper metal layer above both the first-type transistor and the second-type transistor, and a back-side inductor having one or more conductors in a back-side lower metal layer at a back side of the substrate. The front-side inductor, the first-type transistor, and the second-type transistor form a stack directly above the back-side inductor.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

Abstract: A method includes forming a complementary Field-Effect Transistor (CFET) including a first FinFET and a second FinFET. The processes for forming the first FinFET includes forming at least one semiconductor fin having a first total count, and forming a first gate stack on the at least one semiconductor fin. The second FinFET is vertically aligned to the first FinFET. The processes for forming the second FinFET includes forming a plurality of semiconductor fins, wherein the plurality of semiconductor fins have a second total count greater than the first total count, and forming a second gate stack on the plurality of semiconductor fins.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a power rail. The device further includes a carrier substrate bonded to the first interconnect structure and a first heat dissipation layer contacting the carrier substrate.

Abstract: A low thermal budget dielectric material treatment is provided. An example method of the present disclosure includes providing a semiconductor structure, depositing a dielectric material over the semiconductor structure, treating the dielectric material with a gaseous species carried in a supercritical fluid, and after the treating, reducing a thickness of the dielectric material.

Abstract: A method for forming complementary FinFET (CFET) in a stacked configuration includes forming a recess in a stacked fin, growing a first epitaxial structure in the recess, etching the first epitaxial structure to remove a portion of the first epitaxial structure, forming a first isolation structure over the first epitaxial structure, and forming a second epitaxial structure over the first isolation structure. In another method, a dummy gate electrode over the stacked fin is etched, a first gate electrode deposited over the stacked fin, a portion of the first gate electrode recessed, and a second gate electrode formed over the first gate electrode. A CFET device includes a second channel region stacked over a first channel region, associated pairs of epitaxial structures on opposing sides of each of the first and second channel regions, and associated gate electrodes for each of the first and second channel regions.

Abstract: A dipole layer is formed over a semiconductor channel region. A doped gate dielectric layer is formed over the dipole layer. The doped gate dielectric layer contains an amorphous material. Via an annealing process, the amorphous material of the doped gate dielectric layer is converted into a material with at least partially crystal phases. After the doped gate dielectric layer is converted into the layer with partially crystal phases, a metal-containing gate electrode is formed over the doped gate dielectric layer.

Abstract: Embodiments of the present disclosure relate to a SRAM (static random access memory) bit cell. More particularly, embodiments of the present disclosure relate to a single port, 8T SRAM cell with write enhance pass gate transistors. Particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6T SRAM cell. The write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. In some embodiments, the single port, 8T SRAM cell according to the present disclosure may be implemented by stacked complementary FETs. Empty or dummy PMOS transistors in a standard 6T stacked CFET SRAM cell are used as pass gate transistors or write enhance pass gate transistors.

Abstract: Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming an n-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives an n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with an n-dipole dopant profile having a peak located at a high-k/interfacial interface ±0.5 nm.

Abstract: Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k/interfacial interface ±0.5 nm.

Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.

Abstract: A semiconductor structure includes a first device assembly and a second device assembly. Each of the first and second device assembly includes a substrate, a main unit disposed on the substrate and including at least one device, a dielectric unit disposed on the main unit and having an interconnecting surface opposite to the substrate, and an electrically conductive routing disposed in the dielectric unit, electrically connected to the at least one device, and including an end portion. The interconnecting surface of the dielectric unit of the first device assembly is bonded to the interconnecting surface of the dielectric unit of the second device assembly such that the end portion of the electrically conductive routing of the first device assembly is in direct contact with the end portion of the electrically conductive routing of the second device assembly. A method for manufacturing the semiconductor structure are also disclosed.

Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor and a second transistor stacked vertically. A conductive via extends vertically from a first source/drain region of the first transistor past the second transistor. The second transistor includes an asymmetric second source/drain region. The asymmetry of the second source/drain region helps ensure that the second source/drain region does not contact the conductive via.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer over first sidewalls of the gate stack using a first precursor. The first precursor includes a first boron- and nitrogen-containing material having a first hexagonal ring structure, the spacer has a plurality of first layers, and each first layer includes boron and nitrogen.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.