Abstract: An object designator system has a laser light source, and image sensor, a display, and a processor coupled with a non-transitory processor-readable medium storing processor-executable code. The image sensor captures an external scene image. The processor determines a range to an object of interest in the external scene and an exposure delay based on the range. The laser light source emits a laser light pulse into the external scene. The image sensor, based on the exposure delay, captures a laser spot image including laser light pulse reflections, and a spot baseline image of the external scene. The processor determines, based on the laser spot image and the spot baseline image, a location of the laser spot in the external scene and generates a symbol indicative of the location of the laser spot. The processor renders the symbol onto the external scene image to display an integrated image to a user.

Abstract: A method for routing of information between networks of differing security levels may include, but is not limited to: receiving a data packet from a first network having a security classification at a first network node; determining a geographic location of the first network node; applying one or more geographic location-dependent access control rules for the data packet according to the geographic location of the first network node with a guard engine; transferring the data packet to a second network according to compliance of the data packet with the one or more geographic location-dependent access control rules.

Abstract: The present invention is a methodology for developing high-assurance computing elements. The method may comprise one or more of the following steps: (a) receiving a plurality of requirements detailing intended behavior of a high-assurance computing elements; (b) creating a model based on the requirements; (c) generating higher order language (HOL) code based on the model; (d) simulating the behavior of the computing elements from the HOL code; (e) generating test cases based on the model; (f) translating the model into a verification tool-specific format; and (g) formally verifying the model using a verification tool.

Abstract: The present invention is directed to routing information between networks of differing security level. Communication to/from each network is handled by a dedicated Offload Engine (OE). Each OE interfaces to a Guard Engine through a Guard Data Mover (GDM) and includes an interface for connecting to an external network. A first OE receives a data packet from a first network intended to be transmitted to a second network. The Guard Engine analyzes the data packet. The Guard Engine includes an ACL (Access Control List) which are rules data packets must meet before being passed onto a destination network. If allowed, the Guard Engine delivers the data packet to the second network via a second OE utilizing a GDM associated with the first OE and a GDM associated with the second OE. The architecture of the present invention reduces the time and effort needed to attain high-assurance certification.

Abstract: A method and apparatus for improved algorithm and key agility for a cryptosystem, comprising a CAM-type key manager. The key manager uses two memories, an index RAM and a key RAM, to virtualize each algorithm or key using pointers from the index RAM to the key RAM, allowing simple reference to algorithm/key pairs, and to dynamically allocate storage for keys. An autonomous free memory management design improves latency in future key write operations by transforming the search for free location addresses in the key RAM memory into a background task, and employing a free address stack. The index RAM is resizable so that data for a plurality of cryptographic algorithms may be stored dynamically.

Abstract: The present invention is a methodology for developing high-assurance microcode. The method may comprise one or more of the following steps: (a) receiving a plurality of requirements detailing intended behavior of microcode (b) creating a model of microcode behavior; (c) generating microcode based on the model; (d) generating test cases based on the model; (e) simulating the behavior of the microcode; (f) translating the model into a verification tool-specific format; and (g) formally verifying the model using a verification tool.

Abstract: The present invention provides a high speed data encryption architecture in which fabric elements are communicatively coupled to one another via a hardwired interconnect. Each of the fabric elements includes a plurality of wide field programmable gate array (FPGA) blocks used for wide datapaths and a plurality of narrow FPGA blocks used for narrow datapaths. Each of the plurality of wide FPGA blocks and each of the plurality of narrow FPGA blocks are communicatively coupled to each other. A control block is communicatively coupled to each of the fabric elements via the hardwired interconnect to provide control signals to each of the fabric elements. The fabric elements are used to implement cryptographic algorithms.

Abstract: The present invention is a rotating priority queue manager. A rotating priority queue manager in accordance with the present invention may include a plurality of source data channels, a corresponding plurality of processing resources, and an arbitrating interface directing the flow of data from the source channels to the processing resources where the data must flow over a shared data path. The plurality of processing resources may comprise any system of parallel processors where the servicing of input data must be carried out in a manner where there the maximum latency for processing a given data channel is determinable, the arbitration between channels is equal, no input channel may prevent another channel from being serviced, and lower priority processing resources are not prohibited from receiving input data if higher priority processing resources are not currently available or if higher priority data is not currently available.

Abstract: An improved computer architecture and system advantageously combine the beneficial characteristics of a high level object oriented programming language with an optimized processor for efficient application to real time embedded computing problems. Additionally, an improved method for resolving symbolic references in code generated by compiling source code written in an object oriented programming language to the corresponding logical memory addresses stores look-up information with the object itself after the first encounter of a given symbolic reference, whereby the logical memory address information is available for subsequent encounters of the symbolic reference, and whereby no modification of the program instructions containing the symbolic reference is necessary. In a preferred embodiment, the Java™ programming language is used.