Patents by Inventor T.J. O'Dwyer

T.J. O'Dwyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware processors and methods for tightly-coupled heterogeneous computing
    Patent number: 10372668
    Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Chang Yong Kang, Pierre Laurent, Hari K. Tadepalli, Prasad M. Ghatigar, T.J. O'Dwyer, Serge Zhilyaev
  • Multiplier pipelining optimization with a postponed estimation correction
    Patent number: 10216483
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: T. J. O'Dwyer, Pierre Laurent
  • HARDWARE PROCESSORS AND METHODS FOR TIGHTLY-COUPLED HETEROGENEOUS COMPUTING
    Publication number: 20180225255
    Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
    Type: Application
    Filed: January 12, 2018
    Publication date: August 9, 2018
    Inventors: Chang Yong Kang, Pierre Laurent, Hari K. Tadepalli, Prasad M. Ghatigar, T.J. O'Dwyer, Serge Zhilyaev
  • MULTIPLIER PIPELINING OPTIMIZATION WITH A POSTPONED ESTIMATION CORRECTION
    Publication number: 20180107453
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
    Type: Application
    Filed: September 5, 2017
    Publication date: April 19, 2018
    Applicant: Intel Corporation
    Inventors: T.J. O'DWYER, PIERRE LAURENT
  • Hardware processors and methods for tightly-coupled heterogeneous computing
    Patent number: 9870339
    Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Chang Yong Kang, Pierre Laurent, Hari K. Tadepalli, Prasad M. Ghatigar, T. J. O'Dwyer, Serge Zhilyaev
  • Multiplier pipelining optimization with a bit folding correction
    Patent number: 9778910
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: October 3, 2017
    Assignee: INTEL CORPORATION
    Inventors: T. J. O'Dwyer, Pierre Laurent
  • Multiplier pipelining optimization with a postponed estimation correction
    Patent number: 9753692
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: T. J. O'Dwyer, Pierre Laurent
  • HARDWARE PROCESSORS AND METHODS FOR TIGHTLY-COUPLED HETEROGENEOUS COMPUTING
    Publication number: 20160378715
    Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Chang Yong Kang, Pierre Laurent, Hari K. Tadepalli, Prasad M. Ghatigar, T.J. O'Dwyer, Serge Zhilyaev
  • MULTIPLIER PIPELINING OPTIMIZATION WITH A POSTPONED ESTIMATION CORRECTION
    Publication number: 20160283195
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
    Type: Application
    Filed: March 25, 2015
    Publication date: September 29, 2016
    Applicant: Intel Corporation
    Inventors: T.J. O'DWYER, PIERRE LAURENT
  • MULTIPLIER PIPELINING OPTIMIZATION WITH A BIT FOLDING CORRECTION
    Publication number: 20160274866
    Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.
    Type: Application
    Filed: March 20, 2015
    Publication date: September 22, 2016
    Applicant: Intel Corporation
    Inventors: T.J. O'DWYER, PIERRE LAURENT
  • Method and system to automatically generate performance evaluation code for multi-threaded/multi-processor architectures
    Publication number: 20050283756
    Abstract: A development system automatically generates evaluation code to examine performance on target hardware.
    Type: Application
    Filed: June 22, 2004
    Publication date: December 22, 2005
    Inventor: T.J. O'Dwyer