Abstract: A device for rehabilitation of the upper limb includes a frame and an exoskeleton mounted on the frame. The exoskeleton has a first joint coupled to the frame, a first L-shaped connector connecting the first joint to a second joint, a second L-shaped connector connecting the second joint to a third joint, and an attaching member attaching an upper limb of a human subject to the exoskeleton. The first joint is situated above a shoulder of the human subject and has a first axis of rotation substantially coinciding with the horizontal abduction/adduction rotation axis of the shoulder. The second joint is situated behind the shoulder and has a second axis of rotation coinciding with the abduction/adduction rotation axis of the shoulder. The third joint is situated at the side of the shoulder and has a third axis of rotation substantially coinciding with the flexion/extension rotation axis of the shoulder.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A process for fabrication of a multilevel interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to fill the via opening (14) at the bottom of an interconnect channel (24). Selective deposition is enhanced by the use of a nucleation layer (20) which is formed on the bottom of the via opening, without being formed on the sidewalls, by use of directional deposition technique such as inductively coupled plasma (ICP) deposition. Nucleation layer (20) eases requirements of a cleaning operation prior to selective deposition and provides a surface from which void-free selective growth can occur.

Abstract: Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.

Abstract: A method for forming a dielectric layer on a surface of a substrate uses high pressure. A pressure vessel of a high pressure oxidation equipment is heated to a predetermined temperature. The substrate is placed inside the pressure vessel. The pressure vessel is pressurized to a pressure above atmospheric pressure. A flow of an oxidizing gas and a flow of steam are introduced into the pressure vessel, wherein the steam flow is only a fraction of the oxidizing gas flow. The dielectric layer on the surface is formed through an oxidizing reaction of the oxidizing gas and steam with the surface of the substrate, wherein the flow of steam acts in a catalytic-like manner to parabolicly accelerate the oxidizing reaction at the surface.

Abstract: A method of decreasing resistivity in an electrically conductive layer (23) includes providing a substrate (14), using a high density plasma sputtering technique to deposit the electrically conductive layer (23) over the substrate (14), and exposing the electrically conductive layer (23) to an anneal in an ambient comprised of a plasma (21).

Abstract: A process for fabrication of a metallized interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to at least partially fill the via opening (14) at the bottom of an interconnect channel (24). An adhesion layer (36) is deposited to overlie the aluminum layer (34) within the via opening (14), and a second aluminum layer (38) is blanket deposited and planarized to form the inlaid interconnect (42) in the interconnect channel (24).