Patents by Inventor T. Srinivasan

T. Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12008738
    Abstract: A method includes obtaining dual-pixel image data that includes a first sub-image and a second sub-image, and generating an in-focus image, a first kernel corresponding to the first sub-image, and a second kernel corresponding to the second sub-image. A loss value may be determined using a loss function that determines a difference between (i) a convolution of the first sub-image with the second kernel and (ii) a convolution of the second sub-image with the first kernel, and/or a sum of (i) a difference between the first sub-image and a convolution of the in-focus image with the first kernel and (ii) a difference between the second sub-image and a convolution of the in-focus image with the second kernel. Based on the loss value and the loss function, the in-focus image, the first kernel, and/or the second kernel, may be updated and displayed.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: June 11, 2024
    Assignee: Google LLC
    Inventors: Rahul Garg, Neal Wadhwa, Pratul Preeti Srinivasan, Tianfan Xue, Jiawen Chen, Shumian Xin, Jonathan T. Barron
  • Publication number: 20240097989
    Abstract: A system, method, and computer-readable medium for an information technology (IT) ecosystem management and monitoring operation. The IT ecosystem management and monitoring operation includes: executing a sustainability application on a hardware processor of an information handling system; providing an IT ecosystem monitoring and management console, the IT ecosystem monitoring and management console comprising an IT ecosystem sustainability system, the IT ecosystem sustainability system comprising a sustainability component; and, communicating between the sustainability component and the sustainability application to perform an IT environment sustainability operation.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: Dell Products L.P.
    Inventors: Christopher A. Robinette, David O. Garner, John T. Morrison, Preeth K. Srinivasan, Jace W. Files, Karthik Suryanarayanan, Jaegeon Park, Alexis Perkins
  • Publication number: 20230170231
    Abstract: Exemplary substrate processing systems may include a factory interface and a load lock coupled with the factory interface. The systems may include a transfer chamber coupled with the load lock. The transfer chamber may include a robot configured to retrieve substrates from the load lock. The systems may include a chamber system positioned adjacent and coupled with the transfer chamber. The chamber system may include a transfer region laterally accessible to the robot. The transfer region may include a plurality of substrate supports disposed about the transfer region. Each substrate support of the plurality of substrate supports may be vertically translatable. The transfer region may also include a transfer apparatus rotatable about a central axis and configured to engage substrates and transfer substrates among the plurality of substrate supports. The chamber system may also include a plurality of processing regions vertically offset and axially aligned with an associated substrate support.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 1, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Jason M. Schaller, Steve Hongkham, Charles T. Carlson, Tuan A. Nguyen, Swaminathan T. Srinivasan, Khokan Chandra Paul
  • Patent number: 11574826
    Abstract: Exemplary substrate processing systems may include a factory interface and a load lock coupled with the factory interface. The systems may include a transfer chamber coupled with the load lock. The transfer chamber may include a robot configured to retrieve substrates from the load lock. The systems may include a chamber system positioned adjacent and coupled with the transfer chamber. The chamber system may include a transfer region laterally accessible to the robot. The transfer region may include a plurality of substrate supports disposed about the transfer region. Each substrate support of the plurality of substrate supports may be vertically translatable. The transfer region may also include a transfer apparatus rotatable about a central axis and configured to engage substrates and transfer substrates among the plurality of substrate supports. The chamber system may also include a plurality of processing regions vertically offset and axially aligned with an associated substrate support.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jason M. Schaller, Steve Hongkham, Charles T. Carlson, Tuan A. Nguyen, Swaminathan T. Srinivasan, Khokan Chandra Paul
  • Publication number: 20220364231
    Abstract: The present disclosure generally relates to gas inject apparatus for a process chamber for processing of semiconductor substrates. The gas inject apparatus include one or more gas injectors which are configured to be coupled to the process chamber. Each of the gas injectors are configured to receive a process gas and distribute the process gas across one or more gas outlets. The gas injectors include a plurality of pathways, a fin array, and a baffle array. The gas injectors are individually heated. A gas mixture assembly is also utilized to control the concentration of process gases flown into a process volume from each of the gas injectors. The gas mixture assembly enables the concentration as well as the flow rate of the process gases to be controlled.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Inventors: Tetsuya ISHIKAWA, Swaminathan T. SRINIVASAN, Matthias BAUER, Ala MORADIAN, Manjunath SUBBANNA, Kartik Bhupendra SHAH, Errol Antonio C. SANCHEZ, Sohrab ZOKAEI, Michael R. RICE, Peter REIMER
  • Publication number: 20220364229
    Abstract: Embodiments described herein include processes and apparatuses relate to epitaxial deposition. A method for epitaxially depositing a material is provided and includes positioning a substrate on a substrate support surface of a susceptor within a process volume of a chamber body, where the process volume contains upper and lower chamber regions. The method includes flowing a process gas containing one or more chemical precursors from an upper gas inlet on a first side of the chamber body, across the substrate, and to an upper gas outlet on a second side of the chamber body, flowing a purge gas from a lower gas inlet on the first side of the chamber body, across the lower surface of the susceptor, and to a lower gas outlet on the second side of the chamber body, and maintaining a pressure of the lower chamber region greater than a pressure of the upper chamber region.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Inventors: Tetsuya ISHIKAWA, Swaminathan T. SRINIVASAN, Matthias BAUER, Manjunath SUBBANNA, Ala MORADIAN, Kartik Bhupendra SHAH, Errol Antonio C SANCHEZ, Michael R. RICE, Peter REIMER, Marc SHULL
  • Publication number: 20220364261
    Abstract: The present disclosure generally relates to a process chamber for processing of semiconductor substrates. The process chamber includes an upper lamp assembly, a lower lamp assembly, a substrate support, an upper window disposed between the substrate support and the upper lamp assembly, a lower window disposed between the lower lamp assembly and the substrate support, an inject ring, and a base ring. Each of the upper lamp assembly and the lower lamp assembly include vertically oriented lamp apertures for the placement of heating lamps therein. The inject ring includes gas injectors disposed therethrough and the base ring includes a substrate transfer passage, a lower chamber exhaust passage, and one or more upper chamber exhaust passages. The gas injectors are disposed over the substrate transfer passage and across from the lower chamber exhaust passage and the one or more upper chamber exhaust passages.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Inventors: Tetsuya ISHIKAWA, Swaminathan T. SRINIVASAN, Kartik Bhupendra SHAH, Ala MORADIAN, Manjunath SUBBANNA, Matthias BAUER, Peter REIMER, Michael R. RICE
  • Publication number: 20220367216
    Abstract: The present disclosure generally relates to an epitaxial chamber for processing of semiconductor substrates. In one example, the epitaxial chamber has a chamber body assembly. The chamber body assembly includes a lower window and an upper window, wherein chamber body assembly, the lower window and the upper window enclose an internal volume. A susceptor assembly is disposed in the internal volume. The epitaxial chamber also has a plurality of temperature control elements. The plurality of temperature control elements include one or more of an upper lamp module, a lower lamp module, an upper heater, a lower heater, or a heated gas passage.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Inventors: Tetsuya ISHIKAWA, Swaminathan T. SRINIVASAN, Matthias BAUER, Ala MORADIAN, Manjunath SUBBANNA, Kartik Bhupendra SHAH, Kostiantyn ACHKASOV, Errol Antonio C. SANCHEZ, Michael R. RICE, Marc SHULL, Ji-Dih HU
  • Patent number: 11243775
    Abstract: In one embodiment, an apparatus includes: a plurality of registers; a first instruction queue to store first instructions; a second instruction queue to store second instructions; a program order queue having a plurality of portions each associated with one of the plurality of registers, each of the portions having entries to store a state of an instruction, the state comprising an encoding of a use of the register by the instruction and a source instruction queue for the instruction; and a dispatcher to dispatch for execution the first and second instructions from the first and second instruction queues based at least in part on information stored in the program order queue, to manage instruction dependencies between the first instructions and the second instructions. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Andrey Ayupov, Srikanth T. Srinivasan, Jonathan D. Pearce, David B. Sheffield
  • Publication number: 20220028710
    Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body along a first surface of the first lid plate. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of apertures of the plurality of apertures defined through the first lid plate. The systems may include a plurality of isolators. An isolator of the plurality of isolators may be positioned between each lid stack of the plurality of lid stacks and a corresponding aperture of the plurality of apertures defined through the first lid plate. The systems may include a plurality of dielectric plates. A dielectric plate of the plurality of dielectric plates may be seated on each isolator of the plurality of isolators.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Anantha K. Subramani, Yang Guo, Seyyed Abdolreza Fazeli, Nitin Pathak, Badri N. Ramamurthi, Kallol Bera, Xiaopu Li, Philip A. Kraus, Swaminathan T. Srinivasan
  • Patent number: 11188341
    Abstract: In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Jeffrey J. Cook, Srikanth T. Srinivasan, Jonathan D. Pearce, David B. Sheffield
  • Patent number: 10910238
    Abstract: Implementations of the disclosure generally relate to a semiconductor processing chamber and, more specifically, a heated support pedestal for a semiconductor processing chamber. In one implementation, a pedestal assembly is disclosed and includes a substrate support comprising a dielectric material and having a support surface for receiving a substrate, a resistive heater encapsulated within the substrate support, a hollow shaft coupled to a support member of the substrate support at a first end of the shaft, and a thermally conductive material disposed at an interface between the support member and the first end of the shaft.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: February 2, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kaushik Alayavalli, Ajit Balakrishna, Sanjeev Baluja, Amit Kumar Bansal, Matthew James Busche, Juan Carlos Rocha-Alvarez, Swaminathan T. Srinivasan, Tejas Ulavi, Jianhua Zhou
  • Patent number: 10896141
    Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Jeffrey J. Cook, Jonathan D. Pearce, Srikanth T. Srinivasan, Rishiraj A. Bheda, David B. Sheffield, Abhijit Davare, Anton Alexandrovich Sorokin
  • Publication number: 20210013055
    Abstract: Exemplary substrate processing systems may include a factory interface and a load lock coupled with the factory interface. The systems may include a transfer chamber coupled with the load lock. The transfer chamber may include a robot configured to retrieve substrates from the load lock. The systems may include a chamber system positioned adjacent and coupled with the transfer chamber. The chamber system may include a transfer region laterally accessible to the robot. The transfer region may include a plurality of substrate supports disposed about the transfer region. Each substrate support of the plurality of substrate supports may be vertically translatable. The transfer region may also include a transfer apparatus rotatable about a central axis and configured to engage substrates and transfer substrates among the plurality of substrate supports. The chamber system may also include a plurality of processing regions vertically offset and axially aligned with an associated substrate support.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Jason M. Schaller, Steve Hongkham, Charles T. Carlson, Tuan A. Nguyen, Swaminathan T. Srinivasan, Khokan Chandra Paul
  • Patent number: 10791981
    Abstract: A portable biomedical device for detecting ischemic stroke in the brain is provided. The device provides portability and compactness and can accommodate software for resolving blood flow velocity measurements. The device can provide both a diagnostic and a predictive tool for determining the occurrence of an ischemic attack, one such example being transient ischemic attack (TIA) not only at hospital bedside but also in a home environment.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 6, 2020
    Assignee: S SQUARE DETECT MEDICAL DEVICES
    Inventor: Govindarajan T. Srinivasan
  • Publication number: 20200310992
    Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Jeffrey J. Cook, Jonathan D. Pearce, Srikanth T. Srinivasan, Rishiraj A. Bheda, David B. Sheffield, Abhijit Davare, Anton Alexandrovich Sorokin
  • Publication number: 20200310815
    Abstract: In one embodiment, an apparatus includes: a plurality of registers; a first instruction queue to store first instructions; a second instruction queue to store second instructions; a program order queue having a plurality of portions each associated with one of the plurality of registers, each of the portions having entries to store a state of an instruction, the state comprising an encoding of a use of the register by the instruction and a source instruction queue for the instruction; and a dispatcher to dispatch for execution the first and second instructions from the first and second instruction queues based at least in part on information stored in the program order queue, to manage instruction dependencies between the first instructions and the second instructions. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Andrey Ayupov, Srikanth T. Srinivasan, Jonathan D. Pearce, David B. Sheffield
  • Publication number: 20200310817
    Abstract: In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Jeffrey J. Cook, Srikanth T. Srinivasan, Jonathan D. Pearce, David B. Sheffield
  • Publication number: 20200115795
    Abstract: A method for cleaning one or more interior surfaces of a processing chamber includes removing a processed substrate from the processing chamber, and introducing a first cleaning chemistry into the processing chamber to generate a first internal pressure of greater than 1.1 atm within the processing chamber and remove deposited contaminants from the one or more interior surfaces of the processing chamber. The method further comprises removing the cleaning chemistry from the processing chamber.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 16, 2020
    Inventors: Pramit Manna, Swaminathan T. Srinivasan, Timothy J. Franklin
  • Publication number: 20200054267
    Abstract: A portable neuro attack monitoring device is described. The neuro attack monitoring device combined with Coherent Hemodynamic Spectroscopy CHS algorithm offers a unique opportunity to directly resolve blood flow velocity measurements and for the first time apply NIRS+CHS technique for the detection of ischemic strokes and TIA. The device comprises a central hub configured for placement on a central part of a patient's head and a plurality of spokes connected to the central hub and configured for placement on the patient's head over a specific portion of the patient's brain. Each spoke can comprise one or more pairs of light emitting sources and at least one light detector, and the light emitting sources can be configured to inject light into the patient's head, at two or more different wavelengths, over a predetermined period of time.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventor: Govindarajan T. SRINIVASAN