Abstract: Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.

Abstract: Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.

Abstract: A microprocessor, data processing system, and method are disclosed for handling parity errors in an address translation facility such as a TLB. The microprocessor includes a load/store unit configured to generate an effective address associated with a load/store instruction. An address translation unit adapted to translate the effective address to a real address using a translation lookaside buffer (TLB). The address translation unit includes a parity checker configured to verify the parity of the real address generated by the TLB and to signal the load store unit when the real address contains a parity error. The load store unit is configured to initiate a TLB parity error interrupt routine in response to the signal from the translation unit. In one embodiment, the TLB interrupt routine selectively invalidates the TLB entry that contained the parity error. The load/store unit preferably includes an effective to real address table (ERAT) containing a set of address translations.

Abstract: Each match word line driver circuit associated with a content addressable memory (CAM) utilizes a scannable latch for testing. The scannable latches associated with a particular CAM are connected together, scan output of one to scan input of the next, forming a scanning latch chain. In test mode the scannable dynamic latch is used either for testing CAM match circuits or for driving word lines to test the RAM array. Testing CAM match circuits is accomplished by patterning the CAM array with known storage values. The match circuitry then compares an effective address to each storage value and the results are scanned out. Testing the RAM array is performed by driving each word line with a known scan value. Each word line responds the scan value and a sense amplifier outputs a RAM array value based on the word line.

Abstract: A data processing system has a memory bus and a system input/output (I/O) bus including I/O drivers. The memory and I/O buses are controlled by a central processor unit (CPU) for transferring data therebetween and to the I/O drivers. A central clock provides clock signals to the CPU, the memory bus and the I/O bus. The central clock further provides memory and I/O phase alignment signals to the CPU, the alignment signals indicating to the CPU when the start of the CPU clock cycle coincides with the start of a memory bus clock cycle or I/O bus clock signal. Circuit means responsive to the phase alignment and CPU clock signals initiate the transfer of data to the memory and I/O data buses in alternate CPU clock signals to reduce the number of I/O pin switching at any given time thereby reducing the noise and power consumption at the I/O pins and in the system.

Abstract: The mast of a portable earth drilling rig is mounted for pivotal movement between a horizontal transport position and selected drilling positions. A series of radially spaced apart lateral projections on each side of the lower end of the mast are provided with apertures for engaging laterally extending projections disposed on a pair of telescopic braces mounted on the rig frame. The braces may be selectively positioned for automatic engagement with a predetermined pair of projections on the mast whereby the mast, for drilling, may be positioned in the desired angular attitude.