Abstract: Herein disclosed is a device for testing batteries as subjects and a method thereof. The battery testing device comprises a power supply module and a short-circuit sensing module. The power supply module is configured to provide a first testing voltage or a first testing current. The short-circuit sensing module, coupled with the power supply module, is configured to integrate the first testing voltage or current during a first testing period, thereby calculating a first output energy provided by the power supply module. The short-circuit sensing module also determines whether the first output energy exceeds a predetermined energy range; when the range is exceeded, the same module generates an error signal. Wherein the short-circuit sensing module generates an error count by calculating during a second testing period the number of times the short-circuit sensing module generates the error signal.

Abstract: Herein disclosed is a device for testing batteries as subjects and a method thereof. The battery testing device comprises a power supply module and a short-circuit sensing module. The power supply module is configured to provide a first testing voltage or a first testing current. The short-circuit sensing module, coupled with the power supply module, is configured to integrate the first testing voltage or current during a first testing period, thereby calculating a first output energy provided by the power supply module. The short-circuit sensing module also determines whether the first output energy exceeds a predetermined energy range; when the range is exceeded, the same module generates an error signal. Wherein the short-circuit sensing module generates an error count by calculating during a second testing period the number of times the short-circuit sensing module generates the error signal.

Abstract: An ESD protection device includes a substrate of a first conductivity type, a well region of a second conductivity type, a first doped region of the second conductivity type, a second doped region of the first conductivity type, a third doped region of the second conductivity type, a fourth doped region of the first conductivity type. The well region is configured in the substrate. The first doped region is configured in the well region. The second doped region is configured in the well region and surrounding the first doped region. The third doped region is configured in the well region and surrounding the first doped region and the second doped region. The fourth doped region is configured in the well region and under the first doped region and the second doped region. The fourth doped region is coupled with the first doped region and with the second doped region, respectively.

Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.

Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.

Abstract: An ESD protection device includes a substrate of a first conductivity type, a well region of a second conductivity type, a first doped region of the second conductivity type, a second doped region of the first conductivity type, a third doped region of the second conductivity type, a fourth doped region of the first conductivity type. The well region is configured in the substrate. The first doped region is configured in the well region. The second doped region is configured in the well region and surrounding the first doped region. The third doped region is configured in the well region and surrounding the first doped region and the second doped region. The fourth doped region is configured in the well region and under the first doped region and the second doped region. The fourth doped region is coupled with the first doped region and with the second doped region, respectively.

Abstract: An ESD protection device includes a p-well with first protrudent portions, an N-well with second protrudent portions, a P-well/N-well boundary, a PMOS transistor disposed in the N-well, an NMOS transistor disposed in the P-well, first P+ diffusion regions in the first protrudent portions, first N+ diffusion regions in the second protrudent portions, second P+ diffusion regions disposed between the PMOS transistor and the second protrudent portions, second N+ diffusion regions disposed between the NMOS transistor and the first protrudent portions, third P+ diffusion regions disposed between the NMOS transistor, the boundary, and two adjacent second P+ diffusion regions, and third N+ diffusion regions disposed between the PMOS transistor, the boundary, and two adjacent second N+ diffusion regions, wherein the first and second protrudent portions are interlacedly arranged at the boundary.

Abstract: A PG wire routing optimization tool for more efficiently routing PG wires in a layout design of an integrated circuit. The PG wire routing optimization tool analyzes a routing of the wires of a power and ground network for unacceptable IR-drops or electromigration problems. If one or more problems are discovered, the PG wire routing optimization tool determines design constraints for the wires that will correct the identified problems. It then initiates a floor planning tool to implement these corrective design constraints in the floor plan design. The PG wire routing optimization tool may alternately or additionally determine design constraints that will minimize the area of the wiring but will avoid creating new IR-drop or electromigration problems. It will then initiate a floor planning tool to implement these optimizing design constraints in the floor plan design.

Abstract: A PG wire routing optimization tool for more efficiently routing PG wires in a layout design of an integrated circuit. The PG wire routing optimization tool analyzes a routing of the wires of a power and ground network for unacceptable IR-drops or electromigration problems. If one or more problems are discovered, the PG wire routing optimization tool determines design constraints for the wires that will correct the identified problems. It then initiates a floor planning tool to implement these corrective design constraints in the floor plan design. The PG wire routing optimization tool may alternately or additionally determine design constraints that will minimize the area of the wiring but will avoid creating new IR-drop or electromigration problems. It will then initiate a floor planning tool to implement these optimizing design constraints in the floor plan design.

Abstract: A method for forming polysilicon connected deep trench DRAM cell. The method at least includes the following steps. First of all, a substrate is provided. Then, a buried plate drives in the substrate. Then, a capacitor dielectric layer is formed to fill into a lower portion of the deep trench. Next, a dielectric collar layer is formed on a sidewall of the deep trench about the capacitor dielectric layer. Then, a selective growth polysilicon layer is formed to fill into the deep trench of the opening. Then, the shallow trench isolation structure is formed in sidewall of the deep trench. Next, a metal-oxide-semiconductor transistor is formed on the substrate. Next, a spacer is formed on sidewall of the metal-oxide semiconductor transistor. Finally, a polysilicon layer is formed on the metal-oxide-semiconductor transistor.

Abstract: A DRAM circuitry includes a DRAM cell that is connected at a first end to a bit line, at a second end to a plate line, and at a third end to a word line, and a sensing amplifier that is electrically connected to the DRAM cell for refreshing the DRAM cell and reading data from the DRAM cell. The sensing amplifier can change a potential of the bit line and a potential of the plate line to write data into the DRAM cell when the word line is turned on.

Abstract: A sponge mop assembly includes a handle and a frame is pivotally connected to the handle. A sponge is movably connected to the frame and located between two squeezing members on the frame. A lever is pivotally connected to the handle and a link device is connected between the lever and the sponge. A sphere is connected to the handle and rotatably obtained in a neck on the frame so that the handle is positioned at angle relative to the frame. Each squeezing member has an extension extending in a direction away from the sponge so that when the squeezing members are rotated to squeeze the sponge, the extensions squeeze the lower portion of the sponge to remove water in the sponge.