Abstract: A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory cells. The first dielectric layer is disposed on the substrate. The memory cells are stacked on the first dielectric layer. Each of the memory cells includes two first conductive layers and a charge storage structure. The charge storage structure is disposed between the two first conductive layers. The charge storage structures in the vertically adjacent memory cells are separated from each other. The channel layer is disposed on a sidewall of the stacked structure and connected to the substrate. The second dielectric layer is disposed between the channel layer and the first conductive layers.

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.

Abstract: A method for fabricating semiconductor structure is provided. A substrate having a plurality of blocks is provided. Each of the blocks includes a first region and a second region. The first region and the second region are disposed alternately. A plurality of composite layers is formed on the substrate. The top-most layer of the composite layers is patterned. A plurality of composite blocks is formed on the first region of the substrate. The composite layers and the composite blocks on the blocks are removed successively by a removal process. A staircase structure is formed on the substrate.

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate, a plurality of composite layers, and at least one composite pillar. The substrate includes a first region and a second region. The composite layers are disposed on the substrate. Each of the composite layers includes at least one exposed surface and at least one sidewall. At least one staircase structure is formed by the exposed surface and the sidewall. The composite pillar is disposed on the exposed surface of the substrate.

Abstract: A method for fabricating semiconductor structure is provided. A substrate having a plurality of blocks is provided. Each of the blocks includes a first region and a second region. The first region and the second region are disposed alternately. A plurality of composite layers is formed on the substrate. The top-most layer of the composite layers is patterned. A plurality of composite blocks is formed on the first region of the substrate. The composite layers and the composite blocks on the blocks are removed successively by a removal process. A staircase structure is formed on the substrate.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first dielectric layer thereon, and a shallow trench isolation (STI) in the substrate and surrounding the first gate layer and the first dielectric layer; removing the first dielectric layer; forming a first spacer on the sidewall of the STI above the first gate layer; and using the first spacer as mask to remove part of the first gate layer and part of the substrate for forming a first opening while defining a first gate structure and a second gate structure.

Abstract: A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory cells. The first dielectric layer is disposed on the substrate. The memory cells are stacked on the first dielectric layer. Each of the memory cells includes two first conductive layers and a charge storage structure. The charge storage structure is disposed between the two first conductive layers. The charge storage structures in the vertically adjacent memory cells are separated from each other. The channel layer is disposed on a sidewall of the stacked structure and connected to the substrate. The second dielectric layer is disposed between the channel layer and the first conductive layers.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first dielectric layer thereon, and a shallow trench isolation (STI) in the substrate and surrounding the first gate layer and the first dielectric layer; removing the first dielectric layer; forming a first spacer on the sidewall of the STI above the first gate layer; and using the first spacer as mask to remove part of the first gate layer and part of the substrate for forming a first opening while defining a first gate structure and a second gate structure.