Patents by Inventor Ta-Chin Chou

Ta-Chin Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186320
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Application
    Filed: February 14, 2024
    Publication date: June 6, 2024
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Patent number: 11948938
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Patent number: 5102155
    Abstract: A bicycle includes a speed-increasing mechanism interposed between the driving sprocket and the driven sprocket. The speed-increasing mechanism includes a small intermediate sprocket mounted rotatably on the frame of the bicycle, a first chain trained on the driving sprocket and the small intermediate sprocket, a large intermediate sprocket connected securely and coaxially to the small intermediate sprocket, and a second chain trained on the large intermediate sprocket and the driven sprocket. The radius of the small intermediate sprocket is smaller than that of the driving sprocket, while the radius of the large intermediate sprocket is greater than that of the driven sprocket.
    Type: Grant
    Filed: June 6, 1991
    Date of Patent: April 7, 1992
    Inventor: Ta-Chin Chou
  • Patent number: 4713712
    Abstract: A cassette type cleaning device for multi-purpose cleaning of the playing/recording head, erasing head, capstan and pinch roller comprises a universally applicable cotton-tipped cleaning stick held in a tubular retainer which is placed in various types of socket cylinders to meet the requirements of cleaning, namely a first type duo tip retaining socket for cleaning the capstan and pinch roller, an oscillatable second type socket driven through a gear train enpowered from the player/recorders driving spindles for cleaning playing/recording heads, and a third type socket moves with the second type socket through a link connection for cleaning the erasing head.
    Type: Grant
    Filed: June 2, 1986
    Date of Patent: December 15, 1987
    Inventor: Ta-Chin Chou