Patents by Inventor Ta-Chung Ma

Ta-Chung Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system
    Patent number: 7099231
    Abstract: A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a fourth sense amplifier circuit. Each of the sense amplifier circuits is independently controlled. Each queue of the multi-queue system has entries in both the first and second memory blocks. A first queue is accessed by alternately accessing the first and second arrays via the first and third sense amplifier circuits. A second queue is subsequently accessed by alternately accessing the first and second arrays via the second and fourth sense amplifier circuits.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: August 29, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Z. Mo, Ta-Chung Ma, Lan Lin
  • Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system
    Publication number: 20060018170
    Abstract: A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a fourth sense amplifier circuit. Each of the sense amplifier circuits is independently controlled. Each queue of the multi-queue system has entries in both the first and second memory blocks. A first queue is accessed by alternately accessing the first and second arrays via the first and third sense amplifier circuits. A second queue is subsequently accessed by alternately accessing the first and second arrays via the second and fourth sense amplifier circuits.
    Type: Application
    Filed: January 21, 2005
    Publication date: January 26, 2006
    Applicant: Integrated Device Technology, Inc.
    Inventors: Mario Au, Jason Mo, Ta-Chung Ma, Lan Lin