Patents by Inventor Ta-Chung (Terry) Tsai

Ta-Chung (Terry) Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250033458
    Abstract: Disclosed is a hybrid power transmission system including an engine, a power split device, a first electric machine, a second electric machine, a power controller, an energy storage module, and a wheel. The power split device is connected to the engine. The first electric machine is connected to the power split device. The second electric machine is connected to the power split device. The power controller is coupled to the first electric machine and the second electric machine. The energy storage module is coupled to the power controller. The wheel is connected to the second electric machine.
    Type: Application
    Filed: April 16, 2024
    Publication date: January 30, 2025
    Applicant: APh ePower Co., Ltd.
    Inventors: Cheng-Ta Chung, Chien-Hsun Wu, Hsiu-Hsien Su, Shang-Zeng Huang
  • Publication number: 20230183892
    Abstract: A moisture-response deforming fabric includes 40 parts by weight to 70 parts by weight of an ordinary yarn and 30 parts by weight to 60 parts by weight of a moisture-response stretching nylon yarn. A water-vapour permeability index (imt) of the moisture-response deforming fabric is greater than or equal to 0.35 under a measurement of the validation FTTS-FP-161.
    Type: Application
    Filed: July 27, 2022
    Publication date: June 15, 2023
    Inventors: Wei-Hsiang LIN, Po-Hsun HUANG, Jen-Chi CHAO, Ta-Chung AN, Shu-Hui LIN
  • Publication number: 20230094736
    Abstract: The present invention relates to a laser beam shaping apparatus, which comprises a non-rotational symmetrical semiconductor laser source, a collimating mirror and a shaping apparatus. Therefore, the profile of laser light can be shaped, and the intensity of laser light with Gaussian distribution can be adjusted without designing for a specific wavelength, and the luminous efficiency will not be reduced accordingly. In addition, since the present invention uses planar film-coated elements, it has low requirements on size and installation accuracy, which can not only effectively reduce the cost of the apparatus, but also avoid problems of aberration or deformation at the same time.
    Type: Application
    Filed: December 10, 2021
    Publication date: March 30, 2023
    Inventors: Sheng Hsiung CHAN, Yu Ta Chung
  • Patent number: 11424595
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 23, 2022
    Assignee: OEPIC Semiconductors, Inc.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu, Wilson Kyi, James Pao
  • Patent number: 11424597
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) has a substrate formed of GaAs. A pair of mirrors is provided wherein one of the pair of mirrors is formed on the substrate. A tunnel junction is formed between the pair of mirrors.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: August 23, 2022
    Assignee: OEPIC Semiconductors, Inc.
    Inventors: Ping-Show Wong, Jingzhou Yan, Ta-Chung Wu, James Pao, Majid Riaziat
  • Patent number: 11283240
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 22, 2022
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu, Wilson Kyi, James Pao
  • Patent number: 11201251
    Abstract: A photodiode has a substrate. A mesa structure is formed on the substrate, wherein the mesa structure has an n region containing an n type dopant formed on the substrate, an intermediate region positioned on the n region and a p region formed on the intermediate region and containing a p type dopant. A contact is formed on a top surface of the mesa and attached to the p region. The contact is formed around an outer perimeter of the mesa. The mesa has a diameter of 30 um or less.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: December 14, 2021
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu
  • Patent number: 10950712
    Abstract: A semiconductor device comprises a substrate, a gate structure disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate structure. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer disposed on the gate dielectric layer and on the first sidewall of the gate structure. The first insulating layer has a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacers are disposed on the first insulating layer and on the second sidewall, respectively.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 16, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Ming Ma, Hung-Chi Huang, Hsien-Ta Chung
  • Publication number: 20200411703
    Abstract: A photodiode has a substrate. A mesa structure is formed on the substrate, wherein the mesa structure has an n region containing an n type dopant formed on the substrate, an intermediate region positioned on the n region and a p region formed on the intermediate region and containing a p type dopant. A contact is formed on a top surface of the mesa and attached to the p region. The contact is formed around an outer perimeter of the mesa. The mesa has a diameter of 30 um or less.
    Type: Application
    Filed: February 5, 2020
    Publication date: December 31, 2020
    Inventors: YI-CHING PAO, MAJID RIAZIAT, TA-CHUNG WU
  • Patent number: 10840106
    Abstract: A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 17, 2020
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, James Pao, Majid Riaziat, Ta-Chung Wu
  • Publication number: 20200350419
    Abstract: A semiconductor device comprises a substrate, a gate structure disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate structure. The gate structure has a first sidewall and a second sidewall opposite to the first sidewall. A first insulating layer disposed on the gate dielectric layer and on the first sidewall of the gate structure. The first insulating layer has a first bird's beak portion covering a rounded bottom corner of the gate structure. A pair of spacers are disposed on the first insulating layer and on the second sidewall, respectively.
    Type: Application
    Filed: May 30, 2019
    Publication date: November 5, 2020
    Inventors: Chu-Ming Ma, Hung-Chi Huang, Hsien-Ta Chung
  • Publication number: 20200343691
    Abstract: A method of forming a Tunnel Junction (TJ) Vertical Cavity Surface Emitting Laser (VCSEL) array comprises forming a first mirror device on a substrate; forming an active region on the first mirror device; forming a first portion of a second mirror device on the active region; forming a plurality of tunnel junctions on the first portion of the second mirror device; and forming a second portion of the second mirror device through an epitaxial overgrowth, the second portion of the second mirror device covering the plurality of tunnel junctions, wherein individual VCSEL elements of the TJ VCSEL array are electrically connected through the epitaxial overgrowth of the second portion of the second mirror device.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Inventors: MAJID RIAZIAT, YI-CHING PAO, TA-CHUNG WU
  • Publication number: 20200220327
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Inventors: YI-CHING PAO, MAJID RIAZIAT, TA-CHUNG WU, WILSON KYI, JAMES PAO
  • Publication number: 20200118832
    Abstract: A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized
    Type: Application
    Filed: October 7, 2019
    Publication date: April 16, 2020
    Inventors: YI-CHING PAO, JAMES PAO, MAJID RIAZIAT, TA-CHUNG WU
  • Publication number: 20190386464
    Abstract: An opto-electronic device has a backside Vertical Cavity Surface Emitting Laser (VCSEL) device. An optical component is formed on a rear surface of the backside VCSEL device.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 19, 2019
    Inventors: YI-CHING PAO, MAJID RIAZIAT, TA-CHUNG WU, WILSON KYI, JAMES PAO
  • Publication number: 20190252858
    Abstract: A method of forming a Tunnel Junction (TJ) Vertical Cavity Surface Emitting Laser (VCSEL) array comprises forming a first mirror device on a substrate; forming an active region on the first mirror device; forming a first portion of a second mirror device on the active region; forming a plurality of tunnel junctions on the first portion of the second mirror device; and forming a second portion of the second mirror device through an epitaxial overgrowth, the second portion of the second mirror device covering the plurality of tunnel junctions, wherein individual VCSEL elements of the TJ VCSEL array are electrically connected through the epitaxial overgrowth of the second portion of the second mirror device.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 15, 2019
    Inventors: MAJID RIAZIAT, YI-CHING PAO, TA-CHUNG WU
  • Patent number: 10356173
    Abstract: A set of runspaces with active connections are maintained in a pool. A set of timers are set and, based upon the timers, simple commands are submitted through the runspaces, to maintain the connections in an active state. The runspaces with the active connections can then be used from the cache, without having to open a new connection.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: MingChieh (Jackie) Chang, Sheng-Yao (George) Shih, Shu-Yu (Steve) Hu, Ta-Chung (Terry) Tsai, Hsin Hui (Ellen) Huang
  • Publication number: 20190214787
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Application
    Filed: December 4, 2018
    Publication date: July 11, 2019
    Inventors: YI-CHING PAO, MAJID RIAZIAT, TA-CHUNG WU, WILSON KYI, JAMES PAO
  • Patent number: 10290728
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first doped region, a second doped region, a first dielectric layer, a third doped region, a fourth doped region, a second dielectric layer and a conductive layer. The substrate has a first trench in a first area and a second trench in a second area. The first and second doped regions are disposed in the substrate respectively at two side of the first trench. The first dielectric layer is disposed on the sidewall of the first trench. The third doped region is disposed around the second trench. The fourth doped region is disposed in the third doped region at one side of the second trench. The second dielectric layer is disposed on the sidewall and bottom of the second trench. The conductive layer is disposed in the first and second trenches.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: May 14, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Ming Ma, Chun-Yi Lin, Hung-Chi Huang, Hsien-Ta Chung
  • Patent number: 10162492
    Abstract: A link selection area may be provided. When rendering a document comprising a plurality of selectable elements, a selection area may be defined around each of the plurality of selectable elements, such as links. Upon receiving a selection of one of these selection areas, an action associated with the respective selectable element associated with the at least one selection area may be performed.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 25, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Chin-Nan Lee, Yun-Huan Lee, Hsiang-Fu Liu, Ta-Chung Tsai, Shu-Fong Huang