Patents by Inventor Ta-Hsi Chou

Ta-Hsi Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10002833
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: June 19, 2018
    Assignee: MediaTek Inc.
    Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
  • Publication number: 20170263559
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Applicant: MediaTek Inc.
    Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
  • Patent number: 9698102
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 4, 2017
    Assignee: MediaTek Inc.
    Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
  • Publication number: 20160276274
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Inventors: Ching-Chung KO, Tao CHENG, Tien-Yueh LIU, Ta-Hsi CHOU, Peng-Cheng KAO, Ling-Wei KE
  • Patent number: 9379059
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: June 28, 2016
    Assignee: MEDIATEK INC.
    Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke
  • Publication number: 20120043663
    Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Inventors: Ching-Chung Ko, Tao Cheng, Tien-Yueh Liu, Ta-Hsi Chou, Peng-Cheng Kao, Ling-Wei Ke