Abstract: An apparatus and method for processing a differential-type signal transmitted through a pair of data lines. First, a voltage range defined by an upper reference and a lower reference and a logic pattern are provided. Then, the signal is tested to generate logic data responsive to the voltage range. Next, the logic data are utilized to compare with the logic pattern so as to generate a test result when the signal enters a transition cycle.

Abstract: A resistor network which utilizes modulating signals to modulate the resistance value of the individual resistive elements thereof. The resistor network includes a plurality of input terminals and output terminals, and a resistive element and a first switch connected in series with the resistive element is provided between each of the input terminals and output terminals. Each resistive elements includes a plurality of resistors connected in parallel, and a plurality of second switches each of which is connected with a corresponding one of the resistors. An equivalent resistance value of the resistive element is obtained between the input terminal and the output terminal by controlling the on/off states of the second switches through the modulating signals to determine which resistors can be selectively connected with the input terminal and the output terminal.

Abstract: A single-end-input voltage level transfer is provided to transfer a first signal into a second signal. The voltage level transfer has a first, a second, a third, and a fourth transistors, a first inverter, and a second inverter, in which the first transistor is an NMOS transistor and the other three are PMOS transistors. A first transistor source is coupled to the first signal. An input end of the first inverter is coupled to a first transistor drain. An output end of the first inverter is coupled to an input end of the second inverter, which exports the second signal. A second transistor source is coupled to a first power source, and a second transistor drain is coupled to a first transistor gate. A second transistor gate is controlled by a complementary second signal. A third transistor source is coupled to a second power source, and a third transistor drain is coupled to the first transistor gate. A third transistor gate is controlled by the second signal.