Patents by Inventor Ta Hsu

Ta Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9383995
    Abstract: Techniques are disclosed relating to ordering of load instructions in a weakly-ordered memory model. In one embodiment, a processor includes a cache with multiple cache lines and a store queue configured to maintain status information associated with a store instruction that targets a location in one of the cache lines. In this embodiment, the processor is configured to set an indicator in the status information in response to migration of the targeted cache line. The indicator may be usable to sequence performance of load instructions that are younger than the store instruction. For example, the processor may be configured to wait, based on the indicator, to perform a younger load instruction that targets the same location as the store instruction until the store instruction is removed from the store queue. This may prevent forwarding of the value of the store instruction to the younger load and preserve load-load ordering.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: July 5, 2016
    Assignee: Apple Inc.
    Inventors: Pradeep Kanapathipillai, Hari Kannan, Po-Yung Chang, Ming-Ta Hsu, Rajat Goel
  • Patent number: 9166045
    Abstract: In an illustrative embodiment, holes are formed in an insulating layer where the gates of NMOS and PMOS transistors are to be formed; and a hard mask spacer layer is formed on the exposed surfaces. Next, spacers are formed on the sidewalls of the holes by anisotropically etching the spacer layer to remove the portion of the spacer layer exposed at the bottom of each hole while leaving some of the spacer layer formed on the sidewalls of the holes. A high-k dielectric layer is then formed between the spacers; and a metal layer is formed on the high-k dielectric layer. Bulk metal layer is then formed on the metal layer. Chemical mechanical polishing is performed to remove the bulk gate metal down to the insulating layer, thereby isolating individual NMOS and PMOS gate structures.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 20, 2015
    Assignee: Altera Coporation
    Inventors: Che Ta Hsu, Fangyun Richter, Ning Cheng, Jeffrey Xiaoqi Tung
  • Publication number: 20150296609
    Abstract: A multi-circuit layer circuit board includes: two circuit layers formed on a substrate, the same circuit layer including a plurality of signal lines and a plurality of ground reference planes. At least one of the signal lines is formed between any two adjacent ground reference planes. The ground reference planes of one circuit layer are electrically coupled to the ground reference planes of the other circuit layer via a plurality of vias. One of the signal lines of one circuit layer is not overlapped with one signal line of the other circuit layer. The signal lines have a toggle rate higher than 800 MHz.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 15, 2015
    Applicant: SUNPLUS TECHNOLOGY CO., LTD.
    Inventor: Chin-Ta HSU
  • Publication number: 20150178001
    Abstract: A data storage device including a flash memory, a temperature sensor, and a controller. The temperature sensor detects surrounding ambient temperature. The controller reads the temperature sensor to obtain a current temperature parameter at a predetermined time, compares a plurality of write temperatures of the blocks with the current temperature parameter one by one, and writes data stored in at least one first block of the blocks into at least one third block of the blocks, wherein the first block corresponds to at least one first write temperature of the write temperatures, and the difference between the first write temperature and the current temperature parameter is greater than a predetermined value.
    Type: Application
    Filed: October 1, 2014
    Publication date: June 25, 2015
    Inventors: Jieh-Hsin Chien, Hung-Ta Hsu
  • Publication number: 20150169403
    Abstract: A data storage device including a flash memory and a controller. The controller performs a first read operation on the pages of a first block of a first block group, and performs a maintenance process to determine whether the first group read count of the first block group is greater than a read threshold when the first read operation is finished. The controller scans the blocks of the first block group to obtain a plurality of first error bit numbers when the first group read count is greater than the read threshold, and updates the block corresponding to the first error bit number that is greater than an error-bit threshold.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 18, 2015
    Inventors: Chia-Han YEN, Hung-Ta HSU
  • Patent number: 9059722
    Abstract: A method for estimating a sampling delay error between a first analog-to-digital converter (ADC) and a second ADC in a time-interleaved ADC includes: receiving a first digital output signal and a second digital output signal generated from the first ADC and the second ADC based on a same analog input signal, respectively; determining a delay amount according to a predetermined sampling delay between the first ADC and the second ADC and a delay adjusting value, and applying the delay amount delay to the second digital output signal to generate a delayed digital output signal, wherein the delay adjusting value Td is used to estimate the sampling delay error Te; calculating a difference between the first digital output signal and the delayed digital output signal; and feeding back the difference for adjusting the delay adjusting value Td according to the difference.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: June 16, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Hong-Ta Hsu
  • Patent number: 8982993
    Abstract: A method for compensating mismatches of an in-phase signal and a quadrature signal of a transmitter/receiver is provided. The method includes: receiving a plurality of test signals to generate two groups of factors, respectively, where each group of factors is applied to two multipliers utilized for compensating a gain mismatch and a phase mismatch of the in-phase signal and the quadrature signal of the transmitter/receiver; then calculating a delay mismatch of the in-phase signal and the quadrature signal according to the two groups of factors.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 17, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuan-Shuo Chang, Hong-Ta Hsu
  • Patent number: 8944323
    Abstract: A method for locating an item using a cloud server of a data center and an electronic device. The cloud server receives a barcode corresponding to a product from the electronic device and searches a location of the product in a shopping mall. The cloud server calculates a route from a location of the electronic device to the location of the product and shows the route on an electronic map of the shopping mall. The cloud server sends the electronic map with the route to the electronic device.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: February 3, 2015
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Cheng-Ta Hsu
  • Publication number: 20150010109
    Abstract: A method for compensating mismatches of an in-phase signal and a quadrature signal of a transmitter/receiver is provided. The method includes: receiving a plurality of test signals to generate two groups of factors, respectively, where each group of factors is applied to two multipliers utilized for compensating a gain mismatch and a phase mismatch of the in-phase signal and the quadrature signal of the transmitter/receiver; then calculating a delay mismatch of the in-phase signal and the quadrature signal according to the two groups of factors.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Inventors: Yuan-Shuo Chang, Hong-Ta Hsu
  • Publication number: 20150006022
    Abstract: An electronic device determines whether an accident happens to a vehicle according to a change of a speed of the vehicle, or a change of a gradient of the vehicle and location information of the vehicle. The electronic device generates rescue information upon the condition that the accident happens to the vehicle. The electronic device dials a predetermined telephone number and outputs the rescue information when the predetermined telephone number is connected.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 1, 2015
    Inventor: CHENG-TA HSU
  • Patent number: 8921977
    Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 30, 2014
    Assignee: Nan Ya Technology Corporation
    Inventors: Jen Jui Huang, Che Chi Lee, Shih Shu Tsai, Cheng Shun Chen, Shao Ta Hsu, Chao Wen Lay, Chun I Hsieh, Ching Kai Lin
  • Patent number: 8921217
    Abstract: Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Wuu-Cherng Lin, Fangyun Richter, Che Ta Hsu, Wen Sun Wu
  • Publication number: 20140368364
    Abstract: A method for estimating a sampling delay error between a first analog-to-digital converter (ADC) and a second ADC in a time-interleaved ADC includes: receiving a first digital output signal and a second digital output signal generated from the first ADC and the second ADC based on a same analog input signal, respectively; determining a delay amount according to a predetermined sampling delay between the first ADC and the second ADC and a delay adjusting value, and applying the delay amount delay to the second digital output signal to generate a delayed digital output signal, wherein the delay adjusting value Td is used to estimate the sampling delay error Te; calculating a difference between the first digital output signal and the delayed digital output signal; and feeding back the difference for adjusting the delay adjusting value Td according to the difference.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Inventor: Hong-Ta Hsu
  • Patent number: 8912104
    Abstract: An integrated circuit may include a substrate in which transistors are formed. The transistors may be associated with blocks of circuitry. Some of the blocks of circuitry may be configured to reduce leakage current. A selected subset of the blocks of circuitry may be selectively heated to reduce the channel length of their transistors through dopant diffusion and thereby strengthen those blocks of circuitry relative to the other blocks of circuitry. Selective heating may be implemented by coating the blocks of circuitry on the integrated circuit with a patterned layer of material such as a patterned anti-reflection coating formed of amorphous carbon or a reflective coating. During application of infrared light, the coated and uncoated areas will rise to different temperatures, selectively strengthening desired blocks of circuitry on the integrated circuit.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 16, 2014
    Assignee: Altera Corporation
    Inventors: Deepa Ratakonda, Christopher J. Pass, Che Ta Hsu, Fangyun Richter, Wilson Wong
  • Patent number: 8879677
    Abstract: A method for compensating mismatches of an in-phase signal and a quadrature signal of a transmitter/receiver is provided. The method includes: receiving a plurality of test signals to generate two groups of factors, respectively, where each group of factors is applied to two multipliers utilized for compensating a gain mismatch and a phase mismatch of the in-phase signal and the quadrature signal of the transmitter/receiver; then calculating a delay mismatch of the in-phase signal and the quadrature signal according to the two groups of factors.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: November 4, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuan-Shuo Chang, Hong-Ta Hsu
  • Patent number: 8867596
    Abstract: A method and apparatus of calibrating I/Q mismatch of a communication circuit is disclosed. The disclosure employs I/Q test signals respectively including different frequency components to calibrate the frequency-dependent I/Q mismatch existing in the communication system.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: October 21, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chin Su, Hong-Ta Hsu
  • Patent number: 8849228
    Abstract: A receiver having a mixer for mixing a radio frequency signal and a local oscillator signal so as to generate a base band signal, a detecting unit for generating from the base band signal a detection signal that represents an extent of local oscillation leakage, and an adjusting unit coupled electrically to said mixer for outputting a control signal thereto to control a current operating state of said mixer, said adjusting unit being further coupled electrically to said detecting unit, and determining whether there is a reduction in the extent of local oscillation leakage based on the detection signal from said detecting unit. In operation, the adjusting unit maintains an adjusting direction for the control signal upon determining that the extent of local oscillation leakage is reduced, reverses the adjusting direction upon determining that the extent of local oscillation leakage is not reduced, and adjusts the control signal according to the adjusting direction.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: September 30, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hong-Ta Hsu, Ying-Hsi Lin
  • Patent number: 8835265
    Abstract: An insulating layer is formed on a semiconductor substrate; and holes are patterned in the insulating layer where transistor gates are to be formed. A hard mask spacer layer is formed on the upper surface of the insulating layer and the holes. Next, the spacer layer is anisotropically etched to remove the portion of the spacer layer exposed at the bottom of each hole as well as the portion of the spacer layer on the upper surface of the insulating layer. However, the etching process does not remove all of the portion of the spacer layer formed on the substantially vertical sidewalls of the holes. A high-k dielectric layer is then formed on the remaining vertical portion of the spacer layer and on the exposed upper surfaces of the substrate and the insulating layer. A metal layer is then formed on the high-k dielectric layer; and individual gate structures are completed.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: September 16, 2014
    Assignee: Altera Corporation
    Inventors: Che Ta Hsu, Fangyun Richter, Ning Cheng, Jeffrey Xiaoqi Tung
  • Patent number: 8823350
    Abstract: A switching regulator for outputting an output voltage is disclosed. The switching regulator includes an upper gate switch, for turning on and turning off according to an upper gate control signal; a lower gate switch, coupled to the upper gate switch, for turning on and turning off according to a lower gate control signal; and a logic circuit, for generating the lower gate control signal according to a lower gate off signal. The lower gate switch turns off during an activation period of the switching regulator.
    Type: Grant
    Filed: November 11, 2012
    Date of Patent: September 2, 2014
    Assignee: Anpec Electronics Corporation
    Inventors: Hung-Ta Hsu, Hsiang-Chung Chang
  • Publication number: 20140210175
    Abstract: A skateboard includes a board body, a front roller assembly and a rear roller assembly. The front and rear roller assemblies are mounted under a bottom face of the board body. The skateboard further includes an arch contact section. The arch contact section is a raised section disposed on a top face of the board body near the rear end thereof. When a user uses the skateboard, the arch of the user's rear foot is in snug contact with the arch contact section, whereby the foot is in good contact with the board body of the skateboard. The arch contact section also provides antislip effect for the user's foot. By means of the arch contact section, the user can more easily operate/control the skateboard.
    Type: Application
    Filed: January 25, 2013
    Publication date: July 31, 2014
    Inventor: Yung-Ta HSU