Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Abstract: A semiconductor substrate and a semiconductor device are provided in which the substrate includes a plurality of chips. Each of the chips includes at least one array region and at least one periphery region. The semiconductor substrate has a plurality of trenches disposed in the array region and/or the periphery region, wherein a ratio of the depth of the trenches to the thickness of the semiconductor substrate is between 0.001 and 0.008, and the area of all the trenches is between 5% and 90% based on the total area of the semiconductor substrate.

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Abstract: An integrated circuit includes a stack in a stack region and a region outside the stack region. A buttress structure disposed outside the stack includes a fence-shaped, electrically passive element configured to oppose expansion of materials outside the stack region in a direction toward the stack region.

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive interface layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive interface layer.

Abstract: A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.

Abstract: An isolation structure and a method of fabricating the same are provided. The isolation structure includes a buffer layer and an encapsulation layer. The buffer layer is located in a trench of a substrate. The encapsulation layer is located in the trench and encapsulates around the buffer layer, wherein the buffer layer is unexposed and is not in contacted with the trench. A material of the buffer layer is different from a material of the encapsulation layer.

Abstract: A semi-damascene method is described for fabricating wordlines without stringers while maintaining critical cell dimensions when wordline pitch is less than 40 nm. A thin conducting layer protects a storage layer during manufacture, the thin conducting layer then making contact with filled-in conducting material.

Abstract: A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.

Abstract: Measurements of line roughness are separated into groups depending upon pre-layers. Image data collected from similar pre-layer types are considered together in order to separate effects of line roughness from distortion of measurements caused by the pre-layers. The resulting line roughness measurements are used to estimate an aspect of line quality.

Abstract: Measurements of line roughness are separated into groups depending upon pre-layers. Image data collected from similar pre-layer types are considered together in order to separate effects of line roughness from distortion of measurements caused by the pre-layers. The resulting line roughness measurements are used to estimate an aspect of line quality.

Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Abstract: An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.

Abstract: A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer.

Abstract: An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.

Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Abstract: An HDP-CVD system is described, including an HDP-CVD chamber for depositing a material on a wafer, and a pre-heating chamber disposed outside of the HDP-CVD chamber to pre-heat the wafer, before the wafer is loaded in the HDP-CVD chamber, to a temperature higher than room temperature and required in the deposition step to be conducted in the HDP-CVD chamber. The pre-heating chamber is equipped with a heating lamp for the pre-heating. The wafer has been formed with a trench before being pre-heated.

Abstract: An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.