Patents by Inventor Ta-Kang Lo
Ta-Kang Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230335630Abstract: A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.Type: ApplicationFiled: May 11, 2022Publication date: October 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Cheng-Guo Chen, Ta-Kang Lo, Cheng-Han Wu
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Publication number: 20230129579Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.Type: ApplicationFiled: November 16, 2021Publication date: April 27, 2023Applicant: United Microelectronics Corp.Inventors: Hao-Ming Lee, Ta Kang Lo, Tsai-Fu Chen, Shou-Wei Hsieh
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Publication number: 20230048684Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Publication number: 20220181505Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.Type: ApplicationFiled: January 11, 2021Publication date: June 9, 2022Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
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Patent number: 10707305Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.Type: GrantFiled: March 14, 2019Date of Patent: July 7, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
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Patent number: 10607891Abstract: A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.Type: GrantFiled: November 6, 2017Date of Patent: March 31, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jiun-Lin Yeh, Hsueh-Chih Tseng, Chia-Chen Tsai, Ta-Kang Lo
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Publication number: 20190214463Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.Type: ApplicationFiled: March 14, 2019Publication date: July 11, 2019Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
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Patent number: 10276663Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.Type: GrantFiled: July 18, 2016Date of Patent: April 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
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Publication number: 20190115259Abstract: A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.Type: ApplicationFiled: November 6, 2017Publication date: April 18, 2019Inventors: Jiun-Lin Yeh, Hsueh-Chih Tseng, Chia-Chen Tsai, Ta-Kang Lo
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Publication number: 20180122705Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.Type: ApplicationFiled: November 2, 2016Publication date: May 3, 2018Inventors: Tai-You Chen, Cheng-Guo Chen, Kun-Yuan Wu, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo, Shang-Jr Chen
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Patent number: 9960083Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.Type: GrantFiled: November 2, 2016Date of Patent: May 1, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tai-You Chen, Cheng-Guo Chen, Kun-Yuan Wu, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo, Shang-Jr Chen
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Publication number: 20180019341Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.Type: ApplicationFiled: July 18, 2016Publication date: January 18, 2018Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
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Patent number: 9779998Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.Type: GrantFiled: March 6, 2017Date of Patent: October 3, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
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Publication number: 20170221766Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.Type: ApplicationFiled: March 6, 2017Publication date: August 3, 2017Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
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Patent number: 9685520Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.Type: GrantFiled: November 17, 2016Date of Patent: June 20, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shuo-Lin Hsu, Hsin-Ta Hsieh, Chun-Chia Chen, Chen-Chien Li, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
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Patent number: 9634002Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.Type: GrantFiled: February 29, 2016Date of Patent: April 25, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
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Patent number: 8823109Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.Type: GrantFiled: January 9, 2013Date of Patent: September 2, 2014Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8765561Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.Type: GrantFiled: June 6, 2011Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8486795Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.Type: GrantFiled: April 12, 2012Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8404533Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.Type: GrantFiled: August 23, 2010Date of Patent: March 26, 2013Assignee: United Microelectronics Corp.Inventors: Cheng-Yu Ma, Wen-Han Hung, Ta-Kang Lo, Tsai-Fu Chen, Tzyy-Ming Cheng