Patents by Inventor Ta-Pen Guo

Ta-Pen Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127673
    Abstract: A method (of generating a layout diagram) includes: generating one or more first conductive patterns representing corresponding conductive material in the first metallization layer, long axes of the first conductive patterns extending substantially in a first direction; generating a first deep via pattern representing corresponding conductive material in each of the second via layer, the first metallization layer, and the first via layer; relative to the first direction and a second direction substantially perpendicular to the first direction, aligning the first deep via pattern to overlap a corresponding component pattern representing conductive material included in an electrical path of a terminal of a corresponding transistor in the transistor layer; and configuring a size of the first deep via pattern in the first direction to be substantially less than a permissible minimum length of a conductive pattern in the first metallization layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Pen Guo, Li-Chun Tien, Chien-Ying Chen, Lee-Chung Lu
  • Patent number: 11127734
    Abstract: An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 11104573
    Abstract: A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jean-Pierre Colinge, Ta-Pen Guo, Chih-Hao Wang, Carlos H. Diaz
  • Publication number: 20210257388
    Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Ta-Pen GUO, Lee-Chung LU, Li-Chun TIEN
  • Publication number: 20210224457
    Abstract: A semiconductor device includes a first power rail, a second power rail, and a first cell. The first cell has a first first-type active region and a first second-type active region, and a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail. The semiconductor device further includes a second cell having a second first-type active region and a second second-type active region, wherein the second first-type active region extends in a second row and a third row on a first side of the first row and has a first width in the column direction greater than a second width of the first first-type active region in the column direction. The semiconductor device also includes a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.
    Type: Application
    Filed: October 16, 2020
    Publication date: July 22, 2021
    Inventors: TA-PEN GUO, CHIEN-YING CHEN
  • Publication number: 20210224458
    Abstract: A semiconductor device includes a first and a second power rails extending in a row direction, a third power rail extending in the row direction between the first and second power rail, and a first cell arranged between the first second power rails. A cell height of the first cell in a column direction perpendicular to the row direction is equal to a pitch between the first and second power rails. The semiconductor device also includes a second cell arranged between the first and third power rails. A cell height of the second cell in the column direction is equal to a pitch between the first and third power rails. A first active region of the first cell includes a first width in the column direction greater than a second width, in the column direction, of a second active region in the second cell.
    Type: Application
    Filed: October 19, 2020
    Publication date: July 22, 2021
    Inventors: TA-PEN GUO, GURU PRASAD
  • Publication number: 20210203314
    Abstract: A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Nick Samra, Stefan Rusu, Ta-Pen Guo
  • Patent number: 11038052
    Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 11011545
    Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Lee-Chung Lu, Li-Chun Tien
  • Patent number: 10998340
    Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Lee-Chung Lu, Li-Chun Tien
  • Patent number: 10985159
    Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Patent number: 10964691
    Abstract: A method for manufacturing a monolithic three-dimensional (3D) integrated circuit (IC) with junctionless semiconductor devices (JSDs) is provided. A first interlayer dielectric (ILD) layer is formed over a semiconductor substrate, while also forming first vias and first interconnect wires alternatingly stacked in the first ILD layer. A first doping-type layer and a second doping-type layer are transferred to a top surface of the first ILD layer. The first and second doping-type layers are stacked and are semiconductor materials with opposite doping types. The first and second doping-type layers are patterned to form a first doping-type wire and a second doping-type wire overlying the first doping-type wire. A gate electrode is formed straddling the first and second doping-type wires. The gate electrode and the first and second doping-type wires at least partially define a JSD.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Patent number: 10951201
    Abstract: A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nick Samra, Stefan Rusu, Ta-Pen Guo
  • Patent number: 10950540
    Abstract: Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Ming-Hsien Lin
  • Publication number: 20200402899
    Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Inventors: Ta-Pen Guo, Carlos H. Diaz, Jean-Pierre Colinge, Yi-Hsiung Lin
  • Patent number: 10854721
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Publication number: 20200350307
    Abstract: A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first gate track, extending a second portion of the boundary from the first gate track to a second gate track, the second portion being contiguous with the first portion, and extending a third portion of the boundary from the first gate track to the second gate track, the third portion being contiguous with the first portion An active region is positioned in the cell by extending the active region across a third gate track, wherein the first gate track is between the second gate track and the third gate track. The layout diagram is stored on a non-transitory computer-readable medium.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Chien-Ying CHEN, Lee-Chung LU, Li-Chun TIEN, Ta-Pen GUO
  • Publication number: 20200335400
    Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventors: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG
  • Publication number: 20200333987
    Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre COLINGE, Carlos H. DIAZ, Ta-Pen GUO
  • Publication number: 20200313659
    Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Inventors: Ta-Pen GUO, Chi-Lin LIU, Shang-Chih HSIEH, Jerry Chang-Jui KAO, Li-Chun TIEN, Lee-Chung LU