Patents by Inventor Ta-Wei Chen

Ta-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220352152
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Publication number: 20220328358
    Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Publication number: 20220321012
    Abstract: A switching regulator includes a first switch, a second switch, an inductor coupled to the first and second switches, and a control circuit. The control circuit controls the first switch to be ON for an ON time period. Next, the control circuit controls the first and second switches to be OFF for a first dead time period. Next, the control circuit controls the second switch to be ON for a synchronous rectification time period. Next, the control circuit controls the first and second switches to be OFF for a second dead time period. Next, the control circuit controls the second switch to be ON for a zero-voltage-switching pulse time period. Next, the control circuit controls the first and second switches to be OFF for a third dead time period. By the above operations, the first switch achieves soft switching.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 6, 2022
    Inventors: Yong-Cyuan Chen, Tzu-Chen Lin, Yi-Wei Lee, Ta-Yung Yang
  • Publication number: 20220305304
    Abstract: A thermoresponsive facial mask has a non-woven fabric structure with multiple layers, wherein at last one of the layers of the non-woven fabric structure has far-infrared hollow fibers. The far-infrared hollow fibers content far-infrared powers that emit a far-infrared radiation. A formula for the thermoresponsive facial mask has a polyalcohol and a germanium element, which promotes the thermoresponsive facial mask to generate an advantage of forming the warming effect automatically.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 29, 2022
    Inventors: Yi Wei Chen, Kuo Pin Cheng, Wei Hao Lee, Ta Wui Cheng, Ke Yang Chen
  • Patent number: 11455019
    Abstract: A docking system for facilitating a connection of an electronics module to a mating connector comprises first and second rails. Each rail has an elongated guide slot for receiving a corresponding guide portion of the electronics module during sliding movement of the electronics module toward the mating connector. A first elastic structure is located on the first rail. The first elastic structure has a first engagement portion extending into the elongated guide slot of the first rail. A second elastic structure is located on the second rail. The second elastic structure has a second engagement portion extending into the elongated guide slot of the second rail. The first engagement portion and the second engagement portion are configured to engage the guide portions of the electronics module and to resist movement of the guide portions in a direction generally perpendicular to the sliding movement of the electronics module.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 27, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chun Chang, Chia-Chun Chen, Ta-Wei Chen, Zhao-Hong Chen
  • Patent number: 11442356
    Abstract: A multi-layer reflective structure is disposed over the substrate. An amorphous capping layer is disposed over the multi-layer reflective structure. The amorphous capping layer may contain ruthenium, oxygen, niobium, nitrogen, tantalum, or zirconium. An amorphous layer may also be disposed between the multi-layer reflective structure and the amorphous capping layer. The amorphous layer includes amorphous silicon, amorphous silicon oxide, or amorphous silicon nitride.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Chih-Tao Chien, Ming-Wei Chen, Ta-Cheng Lien
  • Publication number: 20220239223
    Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.
    Type: Application
    Filed: December 23, 2021
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220239224
    Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.
    Type: Application
    Filed: January 2, 2022
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220238727
    Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Wu-Te Weng, Chien-Wei Chiu, Ta-Yung Yang
  • Patent number: 11391708
    Abstract: An actuating and sensing module is provided. The actuating and sensing module includes at least one sensor, at least one actuating device and a power storage member. The sensor is disposed for measuring fluid. The actuating device is disposed proximate to the sensor and is disposed for transporting the fluid. The power storage member is configured as a graphene battery and is disposed for providing power to the at least one sensor and the at least one actuating device for driving the at least one sensor and the at least one actuating device. The actuating device is driven to transport the fluid toward the sensor so as to make the fluid measured by the sensor.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: July 19, 2022
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ta-Wei Hsueh, Li-Pang Mo, Shih-Chang Chen, Ching-Sung Lin, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai
  • Publication number: 20220223464
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 14, 2022
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20220224325
    Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.
    Type: Application
    Filed: January 4, 2022
    Publication date: July 14, 2022
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Patent number: 11297733
    Abstract: A flap for a cage for holding electronic devices in a computing system is disclosed. The flap includes a main segment, a first vertical extension, a second vertical extension, a lateral ledge, and a tapered ledge. The first vertical extension and the second vertical extension extend from a first side of the main segment. The lateral ledge extends from a third side of the main segment. The tapered extensions extend from a second side of the main segment and include a flat section and an angled section. The flap has a deployed position and a stored position in the cage. The flap engages with at least two sides of the cage in the deployed or the stored position. The flap may be in the stored position when an electronic component is present. The flap blocks airflow through the cage in the deployed position.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: April 5, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chun Chang, Ta-Wei Chen, Shih-Wei Peng, Yi-Huang Chiu
  • Publication number: 20220071052
    Abstract: A flap for a cage for holding electronic devices in a computing system is disclosed. The flap includes a main segment, a first vertical extension, a second vertical extension, a lateral ledge, and a tapered ledge. The first vertical extension and the second vertical extension extend from a first side of the main segment. The lateral ledge extends from a third side of the main segment. The tapered extensions extend from a second side of the main segment and include a flat section and an angled section. The flap has a deployed position and a stored position in the cage. The flap engages with at least two sides of the cage in the deployed or the stored position. The flap may be in the stored position when an electronic component is present. The flap blocks airflow through the cage in the deployed position.
    Type: Application
    Filed: December 16, 2020
    Publication date: March 3, 2022
    Inventors: Chun CHANG, Ta-Wei CHEN, Shih-Wei PENG, Yi-Huang CHIU
  • Publication number: 20220057849
    Abstract: A docking system for facilitating a connection of an electronics module to a mating connector comprises first and second rails. Each rail has an elongated guide slot for receiving a corresponding guide portion of the electronics module during sliding movement of the electronics module toward the mating connector. A first elastic structure is located on the first rail. The first elastic structure has a first engagement portion extending into the elongated guide slot of the first rail. A second elastic structure is located on the second rail. The second elastic structure has a second engagement portion extending into the elongated guide slot of the second rail. The first engagement portion and the second engagement portion are configured to engage the guide portions of the electronics module and to resist movement of the guide portions in a direction generally perpendicular to the sliding movement of the electronics module.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 24, 2022
    Inventors: Chun CHANG, Chia-Chun CHEN, Ta-Wei CHEN, Zhao-Hong CHEN
  • Publication number: 20210360812
    Abstract: A swing arm lock mechanism for securing a printed circuit board to a bracket includes a main body, a hooked arm, and an aperture in the main body. The hooked arm extends from and is integral with the main body. The hooked arm and main body define an open-ended slot for engaging a lock pin disposed on the bracket. The aperture receives a fastener for securing the main body to the printed circuit board such that the main body and hooked arm can rotate about a central axis of the fastener from a first unlocked position to a second locked position.
    Type: Application
    Filed: August 28, 2020
    Publication date: November 18, 2021
    Inventors: Ta-Wei CHEN, Chia-Chun CHEN, Chun CHANG, Jyue HOU
  • Publication number: 20210320949
    Abstract: A system for and a method of regulating the data interconnections between applications running on an infrastructure are provided. The system/method records access permission data into metadata embedded in the source code of each such application that regulates the data that can be received or transmitted by that application. In addition to regulating the receipt or transmission of data, the metadata can serve to provide instruction to firewalls and other regulating systems in order to configure those systems to allow the applications to receive and transmit data for which permissions have been recorded.
    Type: Application
    Filed: June 2, 2021
    Publication date: October 14, 2021
    Applicant: JPMorgan Chase Bank, N.A.
    Inventors: Ronald W. RITCHEY, Ta-Wei CHEN, Khanh TRAN, David LAURANCE, Cedric Ken WIMBERLEY, Parthasarathi CHAKRABORTY, Aradhna CHETAL, Donald B. ROBERTS
  • Patent number: 11089707
    Abstract: Embodiments disclosed herein provide an apparatus to enable smooth and safe assembly of functional modules to computer chassis. The apparatus includes a chassis and a pair of racks mounted to the chassis. Each rack has a plurality of gear teeth formed thereon. A module having a housing is slidably coupled to the chassis and disposed between the pair of racks. A pair of gear pinions are rotatably mounted to the housing and meshed to the gear teeth of one of the racks. A damping member is coupled between each gear pinion and the housing. A sliding movement of the housing relative to the chassis rotates the pair of gear pinions to roll over along the gear teeth. During the sliding movement of the housing, the damping member exerts a resistance force against the housing, to reduce the movement speed of the housing.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 10, 2021
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Chang-Hsing Lee, Chia-Ching Huang, Ta-Wei Chen, Sung-Feng Chen, Ming Jie Chai
  • Patent number: 11057433
    Abstract: A system for and a method of regulating the data interconnections between applications running on an infrastructure are provided. The system/method records access permission data into metadata embedded in the source code of each such application that regulates the data that can be received or transmitted by that application. In addition to regulating the receipt or transmission of data, the metadata can serve to provide instruction to firewalls and other regulating systems in order to configure those systems to allow the applications to receive and transmit data for which permissions have been recorded.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 6, 2021
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Ronald W. Ritchey, Ta-Wei Chen, Khanh Tran, David Laurance, Cedric Ken Wimberley, Parthasarathi Chakraborty, Aradhna Chetal, Donald B. Roberts
  • Publication number: 20210201435
    Abstract: A graphics processing unit (GPU) server having a GPU host head with one or more host graphics processing units (GPUs). The GPU server further has a GPU system with a plurality of system GPUs that are separate from the host GPUs, and that are configured to rapidly accelerate creation of images for output to a display device. The GPU server also has a mounting assembly that integrates the GPU host head and the GPU system into a single GPU server unit. The GPU host head is independently movable relative to the GPU system.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 1, 2021
    Inventors: Hsiao-Tsu NI, Yaw-Tzorng TSORNG, Chun CHANG, Ta-Wei CHEN