Patents by Inventor Ta-Wei Chou

Ta-Wei Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153890
    Abstract: The semiconductor package substrate module including a substrate, a plurality of first wires, at least one second wire, a chip, and an encapsulating body, wherein the first wires electrically connect to a first electrical contact point of the substrate and a second electrical contact point of the chip. Besides, one end of the at least one second wire connects to the at least one grounding transfer area or a first ground contact point of the substrate, and another end of the second wire extends toward a cutting area. The encapsulating body encapsulates the substrate, the first and second wires, and the chip. The semiconductor package substrate module is cut and separated along the cutting area of the substrate to form a plurality of semiconductor packaging components. A side surface of the encapsulating body exposes the first wires or at least one second wire of each semiconductor packaging component.
    Type: Application
    Filed: March 30, 2023
    Publication date: May 9, 2024
    Inventors: Chia Fong CHOU, Ta Wei CHOU, Hui-Lung HSU
  • Patent number: 11948938
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Patent number: 10133887
    Abstract: A card reader and an electronic protection module thereof are provided. The electronic protection module includes a circuit substrate, a first outer cover, a second outer cover, first communicated pieces, second communicated pieces, a first soft circuit board, and a second soft circuit board. The first soft circuit board covers a magnetic-card signal reading element located on a surface of the circuit substrate, the second soft circuit board covers a chip-card signal reading element located on the other surface of the circuit substrate, and the first outer cover and the second outer cover respectively cover the outside of the first soft circuit board and the outside of the second soft circuit board, to achieve a coating function of a stereoscopic box shape. Two sides of the circuit substrate are covered for protection, so that the card reader having card swiping and card inserting functions is provided with a protection mechanism.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 20, 2018
    Assignee: Uniform Industrial Corp.
    Inventors: Yu-Tsung Chen, Ta-Wei Chou
  • Patent number: D629368
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: December 21, 2010
    Assignee: Everlight Electronics Co., Ltd.
    Inventor: Ta-Wei Chou