Abstract: A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.

Abstract: A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.

Abstract: A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable Idsat characteristics may then be formed.

Abstract: A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable Idsat characteristics may then be formed.

Abstract: A fiber optic fiber Fabry-Perot interferometer diaphragm sensor and method of measurement is provided. A fiber Fabry-Perot interferometer diaphragm sensor (12a, 12b, 12c) includes a base (54a, 54b, 54c) and a diaphragm (52a, 52b, 52c) with an optic fiber (30) coupled under tension between the base (54a, 54b, 54c) and the diaphragm (52a, 52b, 52c). A fiber Fabry-Perot interferometer element (40) is contained within the optic fiber (30) and operates to sense movement of the diaphragm (52a, 52b, 52c). In a particular embodiment, the diaphragm (52a) moves in response to a pressure (P) applied to the diaphragm (52a). In another embodiment, a proof mass (72) is coupled to the diaphragm (52b) such that the diaphragm (52b) moves in response to an acceleration (A). In yet another embodiment, a magnetic body (80) is coupled to the diaphragm (52c) such that the diaphragm (52c) moves in response to a magnetic field (M).

Abstract: A system and method for measuring jitter. One class of embodiments is particularly useful for testing the aperture jitter of a high speed Analog to Digital (A/D) converter. Aperture jitter in a Sample and Hold circuit (S/H) or in an A/D converter introduces noise into the sampled signal, which is more extreme in areas of the input waveform that have a steep positive or negative slope. The preferred embodiment allows an easy and inexpensive way to measure aperture jitter in S/H and A/D circuits. The technique can also be adapted for measuring edge jitter in digital clock signals or in analog sine wave signals.