Abstract: An amplifier including a first routing circuit, an input stage circuit, an output stage circuit, a second routing circuit, and a bias voltage generating circuit is provided. The bias voltage generating circuit generates a first bias voltage and a second bias voltage for respectively supplying a first tail current source and a second tail current source of the input stage circuit. During a first period, the first bias voltage is related to the voltage at a first input terminal of the amplifier, and the second bias voltage is related to the voltage at a second input terminal of the amplifier. During a second period, the first bias voltage is related to the voltage at the second input terminal of the amplifier, and the second bias voltage is related to the voltage at the first input terminal of the amplifier.

Abstract: An amplifier including a first routing circuit, an input stage circuit, an output stage circuit, a second routing circuit, and a bias voltage generating circuit is provided. The bias voltage generating circuit generates a first bias voltage and a second bias voltage for respectively supplying a first tail current source and a second tail current source of the input stage circuit. During a first period, the first bias voltage is related to the voltage at a first input terminal of the amplifier, and the second bias voltage is related to the voltage at a second input terminal of the amplifier. During a second period, the first bias voltage is related to the voltage at the second input terminal of the amplifier, and the second bias voltage is related to the voltage at the first input terminal of the amplifier.

Abstract: MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.

Abstract: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

Abstract: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

Abstract: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

Abstract: A semiconductor device includes a gate stack; an air-gap under the gate stack; a semiconductor layer vertically between the gate stack and the air-gap; and a first dielectric layer underlying and adjoining the semiconductor layer. The first dielectric layer is exposed to the air-gap.

Abstract: MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.

Abstract: MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.

Abstract: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

Abstract: A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.

Abstract: A semiconductor device includes a gate stack; an air-gap under the gate stack; a semiconductor layer vertically between the gate stack and the air-gap; and a first dielectric layer underlying and adjoining the semiconductor layer. The first dielectric layer is exposed to the air-gap.

Abstract: A strained channel transistor can be provided by combining a stressor positioned in the channel region with stressors positioned on opposite sides of the channel region. This produces increased strain in the channel region, resulting in correspondingly enhanced transistor performance.

Abstract: A semiconductor device includes a gate stack; an air-gap under the gate stack; a semiconductor layer vertically between the gate stack and the air-gap; and a first dielectric layer underlying and adjoining the semiconductor layer. The first dielectric layer is exposed to the air-gap.

Abstract: An integrated circuit having high performance CMOS devices with good short channel effects may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature. An integrated circuit having high performance CMOS devices with low parasitic junction capacitance may be made by forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.

Abstract: This disclosure relates to a turbine generator set, in which an axial-flow turbine and a generator are embedded inside a flow channel. In an exemplary embodiment of the disclosure, the turbine generator set comprises: a flow channel being provided with a front end as an inlet duct and a back end as an outlet duct; an axial-flow turbine, being single-stage or multi-stage, capable of transforming thermal and pressure energies of a working fluid inside the flow channel into rotational energy; and a generator, comprising a rotor and a stator, being capable of transforming the rotational energy into electricity. A shaft of the turbine and a shaft of the generator can be coupled directly or by way of a gear set. Electricity is transmitted from the flow channel by way of a bunch of cables passing through the flow channel.

Abstract: A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.

Abstract: A MOS device having reduced recesses under a gate spacer and a method for forming the same are provided. The MOS device includes a gate structure overlying the substrate, a sidewall spacer on a sidewall of the gate structure, a recessed region having a recess depth of substantially less than about 30 ? underlying the sidewall spacer, and a silicon alloy region having at least a portion in the substrate and adjacent the recessed region. The silicon alloy region has a thickness of substantially greater than about 30 nm. A shallow recess region is achieved by protecting the substrate when a hard mask on the gate structure is removed. The MOS device is preferably a pMOS device.

Abstract: A semiconductor device includes a gate stack; an air-gap under the gate stack; a semiconductor layer vertically between the gate stack and the air-gap; and a first dielectric layer underlying and adjoining the semiconductor layer. The first dielectric layer is exposed to the air-gap.

Abstract: A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.