Patents by Inventor Ta-Wen Hung

Ta-Wen Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RC delay detectors with high sensitivity for through substrate vias
    Patent number: 8384430
    Abstract: A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Wei-Pin Changchien, Pei-Ying Lin, Ta-Wen Hung
  • RC Delay Detectors with High Sensitivity for Through Substrate Vias
    Publication number: 20120038388
    Abstract: A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.
    Type: Application
    Filed: December 17, 2010
    Publication date: February 16, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Wei-Pin Changchien, Pei-Ying Lin, Ta-Wen Hung