Patents by Inventor Ta-Yang Lin
Ta-Yang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6941957Abstract: A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.Type: GrantFiled: July 16, 2003Date of Patent: September 13, 2005Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Kuo-Feng Chen, Hsiu-Mei Yu, Charles Tseng, Ta-Yang Lin
-
Patent number: 6784002Abstract: A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist.Type: GrantFiled: June 21, 2002Date of Patent: August 31, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hui-Peng Wang, Kuo-Wei Lin, Hwei-Mei Yu, Ta-Yang Lin, Charles Tseng
-
Patent number: 6696356Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.Type: GrantFiled: December 31, 2001Date of Patent: February 24, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsin Tseng, Hsiu-Mei Yu, Ta-Yang Lin, Fang-Chung Liu, Kai-Ming Ching, Tung-Heng Shie
-
Publication number: 20040013804Abstract: A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.Type: ApplicationFiled: July 16, 2003Publication date: January 22, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Feng Chen, Hsiu-Mei Yu, Charles Tseng, Ta-Yang Lin
-
Patent number: 6624060Abstract: A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.Type: GrantFiled: January 12, 2002Date of Patent: September 23, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Kuo-Feng Chen, Hsiu-Mei Yu, Charles Tseng, Ta-Yang Lin
-
Publication number: 20030134498Abstract: A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.Type: ApplicationFiled: January 12, 2002Publication date: July 17, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.,Inventors: Kuo-Feng Chen, Hsiu-Mei Yu, Charles Tseng, Ta-Yang Lin
-
Publication number: 20030124832Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.Type: ApplicationFiled: December 31, 2001Publication date: July 3, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Hsin Tseng, Hsiu-Mei Yu, Ta-Yang Lin, Fang-Chung Liu, Kai-Ming Ching, Tung-Heng Shie
-
Patent number: 6486054Abstract: The present invention teaches how greater solder ball height can be achieved without the need to sacrifice areal density. The mold in which the solder is formed, is created in two steps. In a first exposure, a negative photoresist (preferably DFR) is patterned to form a conventional cylindrical mold. However, exposure and development time are adjusted in such a way that a layer of unexposed and undeveloped resist of reduced thickness remains covering the floor of the mold. This residual resist layer is given a second exposure and, after development, forms an annular insert in the bottom of the first mold. After the mold has been filled with solder (either through electroplating or by using solder paste) it is removed, the result being a solder bump made up of two contiguous coaxial cylinders the upper one having the larger diameter. After remelt, bumps having this shape form oblate spheroids rather than spheres.Type: GrantFiled: January 28, 2002Date of Patent: November 26, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yang-Tung Fan, Hsiu-Mei Yu, Li-Hsin Tseng, Kuang-Peng Lin, Ta-Yang Lin