Patents by Inventor Taarinya Polepeddi
Taarinya Polepeddi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10719443Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: March 25, 2019Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Patent number: 10691626Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.Type: GrantFiled: May 7, 2019Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Publication number: 20190332556Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: ApplicationFiled: May 7, 2019Publication date: October 31, 2019Inventors: Bill NALE, Raj K. RAMANUJAN, Muthukumar P. SWAMINATHAN, Tessil THOMAS, Taarinya POLEPEDDI
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Publication number: 20190220406Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
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Patent number: 10282322Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.Type: GrantFiled: April 7, 2017Date of Patent: May 7, 2019Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukuman P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Patent number: 10282323Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.Type: GrantFiled: July 26, 2018Date of Patent: May 7, 2019Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Patent number: 10241943Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: GrantFiled: December 29, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Patent number: 10241912Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: March 13, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Publication number: 20190018809Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: ApplicationFiled: July 26, 2018Publication date: January 17, 2019Inventors: Bill NALE, Raj K. RAMANUJAN, Muthukumar P. SWAMINATHAN, Tessil THOMAS, Taarinya POLEPEDDI
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Publication number: 20180189207Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: ApplicationFiled: December 29, 2017Publication date: July 5, 2018Inventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Publication number: 20170249266Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: ApplicationFiled: April 7, 2017Publication date: August 31, 2017Inventors: Bill NALE, Raj K. RAMANUJAN, Muthukuman P. SWAMINATHAN, Tessil THOMAS, Taarinya POLEPEDDI
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Publication number: 20170249250Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: March 13, 2017Publication date: August 31, 2017Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
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Patent number: 9619408Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.Type: GrantFiled: March 25, 2016Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Patent number: 9600416Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: September 30, 2011Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Publication number: 20160210251Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology.Type: ApplicationFiled: March 25, 2016Publication date: July 21, 2016Inventors: Bill NALE, Raj K. RAMANUJAN, Muthukumar P. SWAMINATHAN, Tessil THOMAS, Taarinya POLEPEDDI
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Patent number: 9342453Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.Type: GrantFiled: September 30, 2011Date of Patent: May 17, 2016Assignee: Intel CorporationInventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
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Publication number: 20140129767Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: ApplicationFiled: September 30, 2011Publication date: May 8, 2014Inventors: Raj K Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn N. Hinton
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Publication number: 20140040550Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.Type: ApplicationFiled: September 30, 2011Publication date: February 6, 2014Inventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminatan, Tessil Thomas, Taarinya Polepeddi