Patents by Inventor Tab Stephens

Tab Stephens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070218661
    Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.
    Type: Application
    Filed: March 15, 2006
    Publication date: September 20, 2007
    Inventors: Mehul Shroff, Paul Grudowski, Mark Hall, Tab Stephens
  • Publication number: 20070196988
    Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.
    Type: Application
    Filed: February 23, 2006
    Publication date: August 23, 2007
    Inventors: Mehul Shroff, Mark Hall, Paul Grudowski, Tab Stephens, Phillip Stout, Olubunmi Adetutu
  • Publication number: 20070141770
    Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.
    Type: Application
    Filed: February 16, 2007
    Publication date: June 21, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Douglas Reber, Mark Hall, Kurt Junker, Kyle Patterson, Tab Stephens, Edward Theiss, Srikanteswara Dakshiina-Murthy, Marilyn Wright
  • Publication number: 20070045735
    Abstract: A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, has all of the source/drain contacts away from the fins as much as reasonably possible. The gate contacts extend upward from the top surface of the elevated semiconductor portion. The gate also extends upward from the top surface of the elevated semiconductor portion. The contacts are located between the fins where the gate is below the height of the elevated semiconductor portion so the contacts are as far as reasonably possible from the gate, thereby reducing gate to drain capacitance and providing additional assistance to alignment tolerance.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 1, 2007
    Inventors: Marius Orlowski, Tab Stephens
  • Publication number: 20060220102
    Abstract: A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.
    Type: Application
    Filed: March 18, 2005
    Publication date: October 5, 2006
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Ramachandran Muralidhar, Tab Stephens
  • Publication number: 20060148196
    Abstract: A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
    Type: Application
    Filed: January 3, 2005
    Publication date: July 6, 2006
    Inventors: Voon-Yew Thean, Brian Goolsby, Bich-Yen Nguyen, Thien Nguyen, Tab Stephens
  • Publication number: 20060073698
    Abstract: An etch stop layer located over a plasma enhanced nitride (PEN) layer. Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer may include transistors with improved drive current at a given leakage current. Also, integrated circuits with the PEN layer may exhibit reduced parasitic capacitance.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Jian Chen, Stanley Filipiak, Yongjoo Jeon, Tab Stephens
  • Publication number: 20060063364
    Abstract: A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 23, 2006
    Inventors: Tab Stephens, Brian Goolsby, Bich-Yen Nguyen, Voon-Yew Thean
  • Publication number: 20050277275
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, forming an insulating layer over the semiconductor substrate, forming a conductive layer over the insulating layer, forming a first metal silicide layer over the conductive layer, patterning the conductive layer to form a patterned first layer, wherein the patterned first layer is a part of a control electrode, patterning the first metal silicide layer to form a patterned first metal silicide layer over the control electrode so that the patterned first metal silicide layer remains over the control electrode, and forming a second metal silicide over the patterned metal silicide layer, wherein the second metal silicide layer has a thickness greater than the thickness of first metal silicide layer.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 15, 2005
    Inventors: Dharmesh Jawarani, Tab Stephens
  • Publication number: 20050277276
    Abstract: A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask prior to final wafer patterning. The intermediate and final hard mask materials are chosen to prevent image transfer into an underlying substrate or wafer prior to the final etch process.
    Type: Application
    Filed: May 25, 2004
    Publication date: December 15, 2005
    Inventors: Tab Stephens, Chong-Cheng Fu, Charles King
  • Publication number: 20050205936
    Abstract: A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width is greater than one. The semiconductor device further includes a first material having a first portion and a second portion, the first portion of the first material filling the first portion of the at least one opening. Defects for relaxing strain at an interface between the first material and the substrate material exist only within the first portion of the first material due to the aspect ratio being greater than one. The second portion of the first material is substantially defect free. Furthermore, the second portion of the first material and an overlying second material different than the first material fill the overlying second portion of the at least one opening.
    Type: Application
    Filed: May 25, 2005
    Publication date: September 22, 2005
    Inventors: John Grant, Tab Stephens
  • Publication number: 20050181596
    Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.
    Type: Application
    Filed: April 6, 2005
    Publication date: August 18, 2005
    Inventors: Douglas Reber, Mark Hall, Kurt Junker, Kyle Patterson, Tab Stephens, Edward Theiss, Srikanteswara Dakshiina-Murthy, Marilyn Wright
  • Publication number: 20050101069
    Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.
    Type: Application
    Filed: October 28, 2003
    Publication date: May 12, 2005
    Inventors: Leo Mathew, Rode Mora, Bich-Yen Nguyen, Tab Stephens, Anne Vandooren
  • Publication number: 20050073028
    Abstract: A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width is greater than one. The semiconductor device further includes a first material having a first portion and a second portion, the first portion of the first material filling the first portion of the at least one opening. Defects for relaxing strain at an interface between the first material and the substrate material exist only within the first portion of the first material due to the aspect ratio being greater than one. The second portion of the first material is substantially defect free. Furthermore, the second portion of the first material and an overlying second material different than the first material fill the overlying second portion of the at least one opening.
    Type: Application
    Filed: October 2, 2003
    Publication date: April 7, 2005
    Inventors: John Grant, Tab Stephens
  • Publication number: 20050026338
    Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift, layer that helps, in combination with the organic ARC, to reduce undesired reflection.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 3, 2005
    Inventors: Douglas Reber, Mark Hall, Kurt Junker, Kyle Patterson, Tab Stephens, Edward Theiss, Srikanteswara Dakshiina-Murthy, Marilyn Wright