Abstract: This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.

Abstract: This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.

Abstract: This invention relates generally to devices, systems, and methods for avoiding bubble formation in a fluidic chamber during filling of the fluidic chamber with a liquid. A first and second piece are operatively coupled to form the fluidic chamber. A protrusion protrudes into a volume of the fluidic chamber such that there is a distance of minimal approach between an apex of the protrusion and a surface of the fluidic chamber. The protrusion forms a channel that extends from one of an inlet and the outlet of the fluidic chamber to the protrusion apex. A maximum distance of travel through the fluidic chamber volume exists between the inlet and the outlet. A cross-sectional area of the fluidic chamber volume increases from the protrusion apex to a transverse plane of the fluidic chamber and decreases from the transverse plane to the other one of the inlet and the outlet.

Abstract: This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.

Abstract: This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.

Abstract: This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.

Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device. Problematic areas, within a chip or die and within a wafer, are identified that result from process variation. The variation is identified and characterized, and the location of each site is stored. The sites may be manually entered into a metrology tool or the method will automatically generate a measurement plan. Process variation and electrical impact are used to direct the measurement of within-die and wafer-level integrated circuit locations.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.