Patents by Inventor Taber H. Smith

Taber H. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190076841
    Abstract: This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 14, 2019
    Inventors: Frank B. Myers, III, Clay D. Reber, Taber H. Smith, Faisal S. Maniar
  • Patent number: 8001516
    Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: August 16, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7962867
    Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: June 14, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7757195
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: July 13, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7712056
    Abstract: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: May 4, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Taber H. Smith
  • Publication number: 20090031261
    Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
    Type: Application
    Filed: June 2, 2008
    Publication date: January 29, 2009
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Taber H. SMITH, Vikas MEHROTRA, David WHITE
  • Publication number: 20080216027
    Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.
    Type: Application
    Filed: January 28, 2008
    Publication date: September 4, 2008
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: David White, Taber H. Smith
  • Patent number: 7393755
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: July 1, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7383521
    Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: June 3, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7380220
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: May 27, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7367008
    Abstract: A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: April 29, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7363099
    Abstract: Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device. Problematic areas, within a chip or die and within a wafer, are identified that result from process variation. The variation is identified and characterized, and the location of each site is stored. The sites may be manually entered into a metrology tool or the method will automatically generate a measurement plan. Process variation and electrical impact are used to direct the measurement of within-die and wafer-level integrated circuit locations.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: April 22, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, David White
  • Patent number: 7363598
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: April 22, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7360179
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: April 15, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7356783
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: April 8, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7353475
    Abstract: A pattern-dependent model is used to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variations to the integrated circuit and (b) a lithography or etch process, and an impact is determined of the variations of feature dimensions on electrical characteristics of the integrated circuit. An impact is determined of the topological variations on electrical characteristics of the integrated circuit. An RC extraction tool is used in conjunction with the using of the model and the determining of the impact.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: April 1, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7325206
    Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: January 29, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7243316
    Abstract: A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: July 10, 2007
    Assignee: Praesagus, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7174520
    Abstract: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: February 6, 2007
    Assignee: Praesagus, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7152215
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: December 19, 2006
    Assignee: Praesagus, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White