Abstract: A memory device includes memory cells, driver circuitry, and control circuitry. The driver circuitry is connected to the memory cells. The driver circuitry includes first sense amplifier circuitries connected to first memory cells of the memory cells. The second sense amplifier circuitries are connected to second memory cells of the memory cells. The control circuitry enables the first sense amplifier circuitries and disables the second sense amplifier circuitries based on a read command. First data associated with the first memory cells is output via the first sense amplifier circuitries based on the read command.

Abstract: Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.

Abstract: A memory circuit is disclosed. The memory circuit includes a plurality of bit lines; a plurality of memory cells arranged in columns, each memory cell connected to a pair of bit lines; and a plurality of clamp circuits, each including a first clamp and logic circuit connected to a first bit line and a second clamp and logic circuit connected to a second bit line, where the first clamp and logic circuit is configured to selectively clamp the first bit line in response to the memory circuit operating in a particular mode, and where the second clamp and logic circuit is configured to selectively clamp the second bit line in response to the memory circuit operating in the particular mode.

Abstract: Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

Abstract: Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.