Patents by Inventor Tacíano Perez
Tacíano Perez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11599267Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.Type: GrantFiled: July 29, 2021Date of Patent: March 7, 2023Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
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Patent number: 11442813Abstract: A memory device includes a non-volatile memory to store data, an execution trace buffer, and a media controller. The media controller receives data-modifying commands and adds the data-modifying commands to the execution trace buffer. The media controller executes the data-modifying commands to modify the data stored in the non-volatile memory and detects errors in the data stored in the non-volatile memory. The media controller repeats execution of data-modifying commands from the execution trace buffer in response to detecting an error.Type: GrantFiled: October 11, 2017Date of Patent: September 13, 2022Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ronaldo Rod Ferreira, Taciano Perez
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Patent number: 11294788Abstract: A program is executed on a first computer system and the execution of the program is monitored. A plurality of operation records are created based upon the monitoring, where each operation record is associated with an operation carried out during execution of the program. A first value of a cumulative performance indicator associated with the execution of the program on the first computer system is determined. For each operation record, a value of a performance indicator associated with carrying out the operation on a second computer system is predicted. For an operation record, the value of the performance indicator is predicted based on a performance model associated with carrying out operations on the second computer system. A second value of the cumulative performance indicator is determined, which is associated with execution of the program on the second computer system and is based on the predicted values of the performance indicator.Type: GrantFiled: July 20, 2017Date of Patent: April 5, 2022Assignee: Hewlett-Packard Development Company, L.P.Inventors: Taciano Perez, Tadeu Marchese, Pedro Henrique Garcez Monteiro, Raphael Gay
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Patent number: 11283600Abstract: Examples disclosed herein relate to symmetrically encrypting a master passphrase key. In one implementation, a computing system includes a machine-readable storage medium to store a symmetrically encrypted master passphrase key, an encrypted version of a first passphrase key associated with a second machine-readable storage medium encrypted using the master passphrase key, and an encrypted version of a second passphrase key associated with a third machine-readable storage medium encrypted using the passphrase key. A processing resource may symmetrically encrypt the master passphrase key using an encryption key derived from authentication information and/or decrypt the stored master passphrase key using a decryption key derived from the authentication information.Type: GrantFiled: June 20, 2017Date of Patent: March 22, 2022Assignee: Hewlett-Packard Development Company, L.P.Inventors: Anellena Santos, Diego R. Medaglia, Taciano Perez, Dirceu Ramos, James R. Waldron
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Patent number: 11200466Abstract: In an implementation, a non-transitory machine-readable storage medium stores instructions that when executed by a processor, cause the processor to allocate classifier data structures to persistent memory, read a number of categories from a set of training data, and populate the classifier data structures with training data including training-based, category and word probabilities calculated based on the training data.Type: GrantFiled: October 28, 2015Date of Patent: December 14, 2021Assignee: Hewlett-Packard Development Company, L.P.Inventors: Humberto Cardoso Marchezi, Taciano Perez, Carlos Haas
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Publication number: 20210357118Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.Type: ApplicationFiled: July 29, 2021Publication date: November 18, 2021Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
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Patent number: 11169733Abstract: In some examples, during execution of an application as an application asset is called, an asset map that is stored in a persistent memory device is searched for an asset identifier associated with the application asset. Using this asset identifier, an application asset stored in the persistent memory device is located. The persistent memory device is directly accessed by a processor executing the application. The processor processes the application asset from its location in the persistent memory device.Type: GrantFiled: October 26, 2017Date of Patent: November 9, 2021Assignee: Hewlett-Packard Development Company, L.P.Inventors: Taciano Perez, Pedro Garcez Monteiro, Roberto Bender, Diego Rahn Medaglia
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Publication number: 20210294721Abstract: A program is executed on a first computer system and the execution of the program is monitored. A plurality of operation records are created based upon the monitoring, where each operation record is associated with an operation carried out during execution of the program. A first value of a cumulative performance indicator associated with the execution of the program on the first computer system is determined. For each operation record, a value of a performance indicator associated with carrying out the operation on a second computer system is predicted. For an operation record, the value of the performance indicator is predicted based on a performance model associated with carrying out operations on the second computer system. A second value of the cumulative performance indicator is determined, which is associated with execution of the program on the second computer system and is based on the predicted values of the performance indicator.Type: ApplicationFiled: July 20, 2017Publication date: September 23, 2021Inventors: Taciano Perez, Tadeu Marchese, Raphael Gay, Raphael Gay
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Patent number: 11093136Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.Type: GrantFiled: February 1, 2017Date of Patent: August 17, 2021Assignee: Hewlett-Packard Development Company, L.P.Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
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Patent number: 11079959Abstract: A computing device that includes a plurality of memory devices and firmware to provide a migration data storage option that reserves a portion of a memory device to store, at least, encrypted metadata describing the physical layout information of the memory devices in preparation for migration of the memory devices.Type: GrantFiled: July 12, 2017Date of Patent: August 3, 2021Assignee: Hewlett-Packard Development Company, L.P.Inventors: Diego Rahn Medaglia, Anellena Santos, Taciano Perez, Kimon Berlin
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Publication number: 20210181964Abstract: A computing device that includes a plurality of memory devices and firmware to provide a migration data storage option that reserves a portion of a memory device to store, at least, encrypted metadata describing the physical layout information of the memory devices in preparation for migration of the memory devices.Type: ApplicationFiled: July 12, 2017Publication date: June 17, 2021Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Diego Rahn MEDAGLIA, Anellena SANTOS, Taciano PEREZ, Kimon BERLIN
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Publication number: 20210176053Abstract: Examples disclosed herein relate to symmetrically encrypting a master passphrase key. In one implementation, a computing system includes a machine-readable storage medium to store a symmetrically encrypted master passphrase key, an encrypted version of a first passphrase key associated with a second machine-readable storage medium encrypted using the master passphrase key, and an encrypted version of a second passphrase key associated with a third machine-readable storage medium encrypted using the passphrase key. A processing resource may symmetrically encrypt the master passphrase key using an encryption key derived from authentication information and/or decrypt the stored master passphrase key using a decryption key derived from the authentication information.Type: ApplicationFiled: June 20, 2017Publication date: June 10, 2021Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Anellena SANTOS, Diego R. MEDAGLIA, Taciano PEREZ, Dirceu RAMOS, James R. WALDRON
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Publication number: 20210149589Abstract: In one example in accordance with the present disclosure, a method is described. According to the method, during execution of an application as an application asset is called, an asset map that is stored in a persistent memory device is searched for an asset identifier associated with the application asset. Using this asset identifier, an application asset stored in a persistent memory device is located. The persistent memory device is directly accessed by a processor executing the application. A processor the processes the application asset from its location in the persistent memory device.Type: ApplicationFiled: October 26, 2017Publication date: May 20, 2021Inventors: Taciano Perez, Pedro Garcez Monteiro, Roberto Bender, Diego Rahn Medaglia
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Publication number: 20210141547Abstract: A system includes a server and a computer. The server stores a non-volatile dual in-line memory module (NVDIMM) configuration profile. The computer includes a plurality of NVDIMMs. The computer downloads the NVDIMM configuration profile from the server and applies the NVDIMM configuration profile to the plurality of NVDIMMs.Type: ApplicationFiled: October 31, 2017Publication date: May 13, 2021Inventors: Diego Medaglia, Taciano Perez, Charles Staub, Anellena Satos, Kimon Berlin
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Patent number: 10936045Abstract: Examples disclosed herein relate to updating memory management information to boot an electronic device from a reduced power mode. In one implementation, prior to entering a reduced power mode, an electronic device creates a snapshot of instructions in a logically volatile partition of a partitioned persistent memory and manage the snapshot as a logically persistent partition. Prior to entering a resume mode, the electronic device updates memory management information to remap a portion of the partitioned memory resource including the snapshot to be managed as a logically volatile partition. The electronic device may resume execution from the snapshot.Type: GrantFiled: September 26, 2016Date of Patent: March 2, 2021Assignee: Hewlett-Packard Development Company, L.P.Inventors: Thiago Silva, Carlos Haas, Taciano Perez, Thierry Fevrier
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Patent number: 10860246Abstract: Examples associated with persistent memory updating are described. One example includes receiving a first store instruction associated with a first page of memory in a persistent memory from an application. The first page is copied to a new page of the persistent memory. A virtual address space of the application is updated to a location of the new page in a read-write mode. The first store instruction is executed on the new page. A file mapping in the persistent memory is updated from a location of the first page to the location of the new page, and the virtual address space for the location of the new page is updated to a read-only mode.Type: GrantFiled: December 21, 2016Date of Patent: December 8, 2020Assignee: Hewlett-Packard Development Company, L.P.Inventors: Taciano Perez, Diego Medaglia, Tadeu Marchese
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Patent number: 10848305Abstract: An example non-transitory computer-readable medium includes instructions that, when executed by a processor, cause the processor to receive a request for data. The instructions also cause the processor to determine a region containing the data based on the metadata. The instructions cause the processor to traverse a tree in the metadata to determine key generation information relating a decryption key for the region to a root key.Type: GrantFiled: March 21, 2016Date of Patent: November 24, 2020Assignee: Hewlett-Packard Development Company, L.P.Inventors: Liqun Chen, Boris Balacheff, Fraser Dickin, Taciano Perez, Wagston Staehler, Craig Walrath, James M Mann
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Publication number: 20200233757Abstract: A memory device includes a non-volatile memory to store data, an execution trace buffer, and a media controller. The media controller receives data-modifying commands and adds the data-modifying commands to the execution trace buffer. The media controller executes the data-modifying commands to modify the data stored in the non-volatile memory and detects errors in the data stored in the non-volatile memory. The media controller repeats execution of data-modifying commands from the execution trace buffer in response to detecting an error.Type: ApplicationFiled: October 11, 2017Publication date: July 23, 2020Inventors: Ronaldo Rod Ferreira, Taciano Perez
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Publication number: 20200226300Abstract: A system may include a non-transitory computer readable medium and a processor. Instructions stored on the non-transitory computer readable medium may include instructions to transmit an identifier of a client device to a database. Instructions may further be executable to receive a code from the database indicating that the client device is allowed to boot. Further instructions may be executable by the processor to run an operating system of the client device in response to receiving the code from the database.Type: ApplicationFiled: October 3, 2017Publication date: July 16, 2020Inventors: Tadeu Marchese, José Dirceu Gründler Ramos, Taciano Perez
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Patent number: 10572269Abstract: A non-volatile main memory stores state information of at least one program executing in the system, and metadata indicating whether a system is to be resumed to a prior state on a next start. As part of restarting the system from a mode in which power is removed from the system, the system is resumed to the prior state using the state information stored in the non-volatile main memory, in response to the metadata indicating that the system is to be resumed to the prior state.Type: GrantFiled: April 29, 2014Date of Patent: February 25, 2020Assignee: Hewlett-Packard Development Company, L.P.Inventors: Taciano Perez, Carlos Haas Costa, Joao Claudio Ambrosi, Diego Rahn Medaglia, Mauricio Nunes Porto, Roberto Bender