Abstract: A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided.

Abstract: A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided.

Abstract: A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces.

Abstract: A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided.

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer.

Abstract: A semiconductor package may include an interposer; a first semiconductor chip disposed on a first surface of the interposer and at least one second semiconductor chip disposed at a predefined distance from the first semiconductor chip, a molding part filling spaces between the first semiconductor chip and the at least one second semiconductor chip and having a trench hole formed therein, and a thermal expansion buffer pattern filling the trench hole.

Abstract: Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.

Abstract: Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

Abstract: A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces.

Abstract: A semiconductor package may include an interposer; a first semiconductor chip disposed on a first surface of the interposer and at least one second semiconductor chip disposed at a predefined distance from the first semiconductor chip, a molding part filling spaces between the first semiconductor chip and the at least one second semiconductor chip and having a trench hole formed therein, and a thermal expansion buffer pattern filling the trench hole.

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer.

Abstract: Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

Abstract: Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.

Abstract: A semiconductor package includes a first interposer; first and second semiconductor chips horizontally mounted over the first interposer and electrically connected with the first interposer; and a second interposer disposed over the first and second semiconductor chips and electrically connected with the first and second semiconductor chips, wherein the first semiconductor chip includes a plurality of first through electrodes, and the second semiconductor chip includes a plurality of second through electrodes, and wherein the first through electrodes of the first semiconductor chip and the second through electrodes of the second semiconductor chip are electrically connected with each other through the first and second interposers.

Abstract: A semiconductor chip includes a substrate having a front surface and a back surface opposite the front surface, a conductive column part passing through the substrate from the front surface to the back surface, a cavity formed by removing a part of the back surface around an end portion of the conductive column part such that the end portion of the conductive column part protrudes from the cavity, a first insulation layer formed in the cavity such that a portion of the end portion of the conductive column part is exposed, and a back electrode electrically connected to the exposed end portion of the conductive column part.

Abstract: A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines.

Abstract: A semiconductor chip includes: a first substrate having a first surface and a second surface facing away from the first surface; a first test through silicon via (TSV) passing through the first substrate from the first surface to the second surface; and a conductive protrusion coupled to the first test TSV and protruding from the second surface.

Abstract: A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted.

Abstract: A semiconductor package includes a first interposer; first and second semiconductor chips horizontally mounted over the first interposer and electrically connected with the first interposer; and a second interposer disposed over the first and second semiconductor chips and electrically connected with the first and second semiconductor chips, wherein the first semiconductor chip includes a plurality of first through electrodes, and the second semiconductor chip includes a plurality of second through electrodes, and wherein the first through electrodes of the first semiconductor chip and the second through electrodes of the second semiconductor chip are electrically connected with each other through the first and second interposers.

Abstract: Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.