Patents by Inventor Tachihisa Yamaguchi

Tachihisa Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MOS type field effect transistor and manufacturing method thereof
    Patent number: 5312767
    Abstract: A MOS type field effect transistor includes a columnar insulation layer (22) formed in a concave portion of semiconductor layer (23) that is formed on a main surface of a semiconductor substrate (21). One source drain region (15) is formed annularly in the main surface of the substrate (21) and outwardly from an outer circumferential surface of the semiconductor layer (23), and is connected to one end of a channel (24) of the semiconductor layer (23). A second source drain region (16) is formed on an upper end of the semiconductor layer (23), and is connected to the other end of the channel (24). A cylindrical gate electrode (28) is formed to surround the outer circumferential surface of the semiconductor layer (23). Insulation layer (22) within semiconductor layer (23) constitutes a vertical SOI device.
    Type: Grant
    Filed: January 26, 1993
    Date of Patent: May 17, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masahiro Shimizu, Tachihisa Yamaguchi
  • Vertical silicon-on-insulator (SOI) MOS type field effect transistor
    Patent number: 5225701
    Abstract: A MOS type field effect transistor includes a columnar insulation layer (22) formed in a concave portion of semiconductor layer (23) that is formed on a main surface of a semiconductor substrate (21). A first source or drain area (25) is formed annularly in the main surface of the substrate (21) and outwardly from an outer circumferential surface of the semiconductor layer (23), and is connected to one end of a channel (24) of the semiconductor layer (23). A second source or drain area (26) is formed on an upper end of the semiconductor layer (23), and is connected to the other end of the channel (24). A cylindrical gate electrode (28) is formed to surround the outer circumferential surface of the semiconductor layer (23). Insulation layer (22) within semiconductor layer (23) constitutes a vertical SOI device.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: July 6, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masahiro Shimizu, Tachihisa Yamaguchi