Abstract: An apparatus and method for arithmetic addition/subtraction of first and second floating point operands, each having a fraction portion and an exponent, includes an alignment circuit, an addition/subtraction-and-rounding-off circuit, and a normalization circuit. The alignment circuit aligns the fraction portions of the first and second operands based on a difference of their exponents obtained by comparing the respective exponents of the first and second operands. The addition/subtraction-and-rounding-off circuit performs at least two addition/subtraction operations between the aligned fraction portions of the first and second operands, and selectively outputs a result value of one of the addition/subtraction operations as a rounded-off result value in response to a rounding-off control signal so that the rounded-off result value is a rounded-off value of addition/subtraction of the fraction portions of the first and second operands.

Abstract: A parallel multiplier by a skip array and a modified Wallace tree utilizes a modified Booth's encoder for encoding a multiplier according to a modified Booth's algorithm, a skip array for partial products, a modified wallace tree for adding binary bits, and a hybrid prefix adder for adding the final two lines. Fast multiplication of 0 (log n) is continuously performed without a standby state of a carry output and the regularity of the arrangement of the parallel multiplier is improved so that its chip area and manufacturing cost are reduced.