Abstract: Provided are a method and apparatus for decoding a mixed code that is a combination of first and second code images. In the method, a mixed code image is obtained by receiving the original image having the mixed code image and removing noise from the original image. Next, the colors, shades, and brightnesses of pixels of the mixed code image are categorized into groups based on a predetermined threshold, the mixed code image is divided into first and second code images, and first and second information are extracted by decoding the first and second code images, respectively. The first and second code images can be effectively decoded by decoding interpretation information, construction information, error control information, and code direction information stored in the first and/or second code images.

Abstract: A mixed code, and a method and apparatus for encoding the same are provided. The mixed code includes a first code image region storing a first code image obtained by encoding first information using color, shading, or a combination thereof, and a second code image region storing a second code image obtained by encoding second information using color, shading, or a combination thereof. The first code image and/or the second code image includes the results of encoding interpretation information, construction information, error control information, and code direction information. The mixed code is made by adjusting the difference in color and brightness between the first and second code images to a predetermined level and combining these images.

Abstract: A method for determining a transmission time of collected context information at a sensor node in a communication system that includes a client, at least one sensor node collecting context information, and an access point (AP) forwarding the context information received from the sensor node to the client. The communication system operates in a session layer of protocol layers of open systems interconnection (OSI). The sensor node calculates a transmission period in which the collected context information is transmitted, and randomly determines a transmission time at which the context information is transmitted within the calculated transmission period. Since the collected context information is transmitted at the transmission time randomly determined by the sensor node, the load on the AP can be balanced.

Abstract: A rendering apparatus and method are provided. The rendering method includes: reading a block, corresponding to a fragment, from among compressed blocks stored in a depth buffer, by considering frequency information corresponding to the fragment and prepared in advance; and performing a depth test for the fragment by considering the restored block.

Abstract: A hybrid tag interface system and an interfacing method therefor are provided. First codes for an object from a wireless recognition tag containing the first codes are received through wireless communication, a second code for the object from an image tag expressing the second code by using a 1- or 2-dimensional image is read through optical contact, and then information on the object is calculated from the first codes and the second code based on their correlation. By doing so, automatic recognition and visibility can be maximized using the hybrid tag combining a wireless recognition tag and an image tag.

Abstract: Provided is a method of classifying colors of a color based image code. The colors of each cell forming the color based image code are classified by sampling a predetermined number of pixels from each cell and then applying a max channel based clustering method, a white balance based color clustering method, a single-linkage algorithm based color classification method, a K-means algorithm based color classification method, or the like. Accordingly, the colors of an image code can be accurately recognized despite of a color distortion due to characteristics of a camera, a printing medium, etc.

Abstract: A rendering method, medium and apparatus for sequentially performing one or more third raster operations to test whether a fragment can be displayed as a pixel after sequentially performing one or more second raster operations to test whether the fragment can be displayed as the pixel, so as to provide efficient power consumption and rapid completion of rendering.

Abstract: A system, method and medium renders an object into a 3-dimensional (3D) graphic image. The rendering system includes a polygon processing unit to calculate a plurality of LOD values of a plurality of fragments corresponding to a plurality of vertices of a predetermined polygon, among a plurality of fragments constructing the predetermined polygon, a span conversion unit to interpolate a plurality of LOD values of remaining fragments apart from the plurality of fragments corresponding to the vertices of the predetermined polygon, using the calculated LOD values, and a texture mapping unit to map one of a plurality of textures with various resolutions to a corresponding fragment of the fragments constructing the predetermined polygon, on the basis of the LOD values interpolated by the span conversion unit.

Abstract: A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about ? in comparison to the existing pipelined divider.

Abstract: A method for determining a transmission time of collected context information at a sensor node in a communication system that includes a client, at least one sensor node collecting context information, and an access point (AP) forwarding the context information received from the sensor node to the client. The communication system operates in a session layer of protocol layers of open systems interconnection (OSI). The sensor node calculates a transmission period in which the collected context information is transmitted, and randomly determines a transmission time at which the context information is transmitted within the calculated transmission period. Since the collected context information is transmitted at the transmission time randomly determined by the sensor node, the load on the AP can be balanced.

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.

Abstract: An apparatus and method for recognizing a code from a code image that is expressed physically or electronically and extracting data represented in the code image is provided. The method includes the steps of receiving a raw image in which a code image is contained, detecting a background image included in the raw image, extracting a code image region in which a background image is excluded, recognizing the shape and type of the code image and the color or shade represented in each of cells, converting the color or shade recognized from each of the cells into a corresponding character, number, or symbol and generating code data. The code image in which predetermined data are represented as colors or shades are received, and original colors or shades can be precisely discriminated regardless of an environment in which the code image is recognized.

Abstract: An apparatus and method for recognizing a code from a code image that is expressed physically or electronically and extracting data represented in the code image is provided. The method includes the steps of receiving a raw image in which a code image is contained, detecting a background image included in the raw image, extracting a code image region in which a background image is excluded, recognizing the shape and type of the code image and the color or shade represented in each of cells, converting the color or shade recognized from each of the cells into a corresponding character, number, or symbol and generating code data. The code image in which predetermined data are represented as colors or shades are received, and original colors or shades can be precisely discriminated regardless of an environment in which the code image is recognized.

Abstract: A method and a device of consistency buffer for a high performance 3D graphic accelerator is disclosed to retain consistency without detecting any overlapping region in advance but determining an overlapping with respect to a rendered pixel.

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.

Abstract: A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

Abstract: A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about ⅓ in comparison to the existing pipelined divider.

Abstract: A 3D graphic accelerator and a method for processing a graphic acceleration using the same is provided in which the inputted primitives are geometrically processed, and existence of any transparent primitives or dominance/rarity of opaque primitives is determined among the geometrically processed primitives. The primitives are rendered in an object-order style and an image-order style in accordance with the determination. The information on the rendered primitives is stored in a corresponding frame buffer and a bucket, and the rendered primitives are display-refreshed. Thus, the 3D graphic accelerator with order- independent transparency and high performance is obtained.