Abstract: A delay line includes a first delay cell and a second delay cell. The first delay cell inverts an input signal to generate a first output signal. The second delay cell inverts the first output signal to generate a second output signal. The driving forces of the first delay cell is adjusted on the basis of a delay control voltage and the second output signal.

Abstract: A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.

Abstract: Disclosed is a display device. The display device may use one transmission line to perform bidirectional data transmission between a timing controller and a source driver. Furthermore, the display device may control the timing controller to transmit a Tx signal to the source driver and control the source driver to transmit correction data, through one transmission line.

Abstract: Disclosed is an apparatus and method for transmitting a display signal having a protocol including a dummy signal and a clock signal. The apparatus for transmitting a display signal may include: a transmitter configured to transmit a display signal in which a dummy signal and a clock signal are sequentially embedded between image data; and a receiver configured to receive the display signal. Since a sufficient margin can be secured before and after the point of time that the clock signal is extracted between the image data, a stable operation of the system can be guaranteed, and the system interface can prevent the occurrence of EMI.

Abstract: Disclosed is a source driver for a display apparatus which is insensitive to power noise, and a configuration of filtering an influence of power noise, which is introduced from an exterior of the source driver or occurs in an interior thereof, to an operation of the source driver. The present invention is applied to the case of receiving a clock signal and a data signal through the single signal line, and is embodied such that a source driver for driving a display apparatus for achieving a high speed operation and a large screen has a characteristic insensitive to power noise.

Abstract: The present invention relates to a source driver of a display apparatus, and relates to a source driver for display apparatus insensitive to power noise, which forcibly decides an internal operation state as normality in a specific period including a power noise generation period and operates insensitively to the power noise. Accordingly, the display apparatus can normally output an image voltage even though power noise occurs.

Abstract: Disclosed is an apparatus and method for transmitting a display signal having a protocol including a dummy signal and a clock signal. The apparatus for transmitting a display signal may include: a transmitter configured to transmit a display signal in which a dummy signal and a clock signal are sequentially embedded between image data; and a receiver configured to receive the display signal. Since a sufficient margin can be secured before and after the point of time that the clock signal is extracted between the image data, a stable operation of the system can be guaranteed, and the system interface can prevent the occurrence of EMI.

Abstract: Disclosed is a display device. The display device may use one transmission line to perform bidirectional data transmission between a timing controller and a source driver. Furthermore, the display device may control the timing controller to transmit a Tx signal to the source driver and control the source driver to transmit correction data, through one transmission line.

Abstract: A clock recovery circuit for recovering a clock signal from a clock-embedded data signal, a data receiving device for recovering a clock signal and a data signal from a clock-embedded data signal, and a data transmitting and receiving system for improving the protocol of a clock-embedded data signal. The data transmitting and receiving system includes a data transmitting device configured to transmit a clock-embedded data signal in which an embedded clock signal is embedded in a data signal; and a data receiving device configured to recover a clock signal corresponding to the embedded clock signal from the clock-embedded data signal.

Abstract: The present invention relates to an output voltage stabilization circuit. Specifically, the present invention relates to an output voltage stabilization circuit of a display device driving circuit, which generates a reference current dependent on a high source voltage using a current source independent of a magnitude of the high source voltage, generates a reference current dependent on a low source voltage using a current source independent of a magnitude of the low source voltage, and then generates a control signal by comparing the magnitudes to each other, whereby the output voltage stabilization circuit may stabilize an output voltage regardless of an order in which the low source voltage and the high source voltage are turned off in a circuit using both the low source voltage and the high source voltage.

Abstract: A clock recovery circuit for recovering a clock signal from a clock-embedded data signal, a data receiving device for recovering a clock signal and a data signal from a clock-embedded data signal, and a data transmitting and receiving system for improving the protocol of a clock-embedded data signal. The data transmitting and receiving system includes a data transmitting device configured to transmit a clock-embedded data signal in which an embedded clock signal is embedded in a data signal; and a data receiving device configured to recover a clock signal corresponding to the embedded clock signal from the clock-embedded data signal.

Abstract: The present invention relates to a source driver of a display apparatus, and relates to a source driver for display apparatus insensitive to power noise, which forcibly decides an internal operation state as normality in a specific period including a power noise generation period and operates insensitively to the power noise. Accordingly, the display apparatus can normally output an image voltage even though power noise occurs.

Abstract: Disclosed is a source driver for a display apparatus which is insensitive to power noise, and a configuration of filtering an influence of power noise, which is introduced from an exterior of the source driver or occurs in an interior thereof, to an operation of the source driver. The present invention is applied to the case of receiving a clock signal and a data signal through the single signal line, and is embodied such that a source driver for driving a display apparatus for achieving a high speed operation and a large screen has a characteristic insensitive to power noise.

Abstract: Embodiments of the present invention provide a method and apparatus for transmitting data between a timing controller and a source driver. In some embodiments, the method includes a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.

Abstract: The present invention relates to an output voltage stabilization circuit. Specifically, the present invention relates to an output voltage stabilization circuit of a display device driving circuit, which generates a reference current dependent on a high source voltage using a current source independent of a magnitude of the high source voltage, generates a reference current dependent on a low source voltage using a current source independent of a magnitude of the low source voltage, and then generates a control signal by comparing the magnitudes to each other, whereby the output voltage stabilization circuit may stabilize an output voltage regardless of an order in which the low source voltage and the high source voltage are turned off in a circuit using both the low source voltage and the high source voltage.

Abstract: Disclosed is a method and apparatus for transmitting data between a timing controller and a source driver, and more particularly, a data transmission method and apparatus between a timing controller and a source driver, which has a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.

Abstract: A hybrid tag interface system and an interfacing method therefor are provided. First codes for an object from a wireless recognition tag containing the first codes are received through wireless communication, a second code for the object from an image tag expressing the second code by using a 1- or 2-dimensional image is read through optical contact, and then information on the object is calculated from the first codes and the second code based on their correlation. By doing so, automatic recognition and visibility can be maximized using the hybrid tag combining a wireless recognition tag and an image tag.

Abstract: A method, medium, and system of rendering image data, including receiving three-dimensional space data for each pixel forming the image data, the three-dimensional space data including depth and color information values for each pixel, determining an order of rendering for a plurality of surfaces forming the image data in an order of the distance between a rendering viewpoint and the surface forming the image data, generating splat depth information values for each splat included in the surface forming the image data, according to the rendering order, and determining whether the splat included in the surface forming the image data is required to be blended and accordingly selectively performing a blending on the splat.

Abstract: A method and device for generating and decoding an image code without a direction finder pattern are provided. In the method of generating an image code, a two-dimensional image is generated by encoding the configured basic information and the error correction information, and disposing the encoded basic and error correction information in predetermined regions, respectively. It is determined whether the two-dimensional image can be decoded for directions which are different from a basic direction of the two-dimensional image, respectively, and the two-dimensional image is output as a physical or electronic image code when a result from decoding for the directions which are different from the basic direction of the two-dimensional image is the same as a decoding result for the basic direction, or when decoding cannot be performed for a direction which is different from the basic direction.

Abstract: A multiple code service system and method thereof are provided. A tag includes first identification information, and a terminal identifies the first identification information of the tag. A service server receives the first identification information and second identification information of the terminal from the terminal, and retrieves the associated contents or service by using the received first and second identification information as key values, and provides the retrieved contents or services. Accordingly, terminals which identify the same tag are provided with different contents or services.