Patents by Inventor Tad Grider

Tad Grider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7572693
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: August 11, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. McKee
  • Publication number: 20090045472
    Abstract: A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm?3. A gate dielectric is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions. A nitrogen-doped electrode including polysilicon is located over the gate dielectric. The electrode has a concentration of nitrogen therein greater than the concentration of nitrogen in the source/drain regions.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 19, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, Narendra Singh Mehta, Rajesh Khamankar, Ajith Varghese, Malcolm J. Bevan, Tad Grider
  • Publication number: 20060270140
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Inventors: F. Scott Johnson, Tad Grider, Benjamin McKee
  • Publication number: 20060270139
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Inventors: F. Scott Johnson, Tad Grider, Benjamin McKee
  • Patent number: 7098098
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: August 29, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. Mckee
  • Patent number: 6682994
    Abstract: Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: January 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. Mckee
  • Publication number: 20030194851
    Abstract: Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.
    Type: Application
    Filed: April 16, 2002
    Publication date: October 16, 2003
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. McKee
  • Publication number: 20030194849
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
    Type: Application
    Filed: August 23, 2002
    Publication date: October 16, 2003
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. McKee