Abstract: An access instruction pipeline for receiving an access instruction for accessing data to be inputted to the pipeline of a vector processor includes a plurality of buffers for buffering a memory request and sending it to a storage control unit, and a detector for judging at the last stage of the plurality of buffers if an instruction is an access instruction or a serialization instruction for serializing the memory access instructions among access instruction pipelines. If a serialization instruction is detected at the last stage of a pipeline, the pipelining operation is stopped, but instructions are filled up in the stopped pipeline. After a serialization instruction has been detected at the last stage of all the pipeline, a pipelining operation starts again.

Abstract: A storage control device is connected between a number of access request control units and a storage device including a number of memory units. The apparatus includes a number of transmission units, each corresponding to one of the access request control unit. Each transmission unit receives access requests from its associated access request control unit and divides the access requests into a number of groups in the order of issuance from the access request control units. The transmission units also add access request identifiers to the access requests in each group and transmit a number of access requests with access request identifiers to a number of access request deciders. Each access request decider is associated with one of the independently accessible memory units. Each decider receives the access requests directed to its associated memory unit and serially supplies the requests to that memory unit.