Patents by Inventor Tadaaki Kariya

Tadaaki Kariya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7193319
    Abstract: A semiconductor device is provided, in which buffer layers having a coefficient of linear expansion of 3×10?6/° C. to 8×10?6/° C. are joined to upper and lower surfaces of a silicon chip through a Pb-free solder having a thickness of not more than 0.05 mm and a melting point of not less than 250° C. The upper surface of the upper buffer layer and the lower surface of the lower buffer layer are respectively joined to a lead and a base through Pb-free solders having a thickness of not less than 0.15 mm and a melting point of not less than 250° C.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: March 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Koji Sasaki, Shinji Hiramitsu, Tadaaki Kariya, Satoshi Matsuyoshi, Ryouichi Kajiwara, Shosaku Ishihara
  • Publication number: 20060214291
    Abstract: A semiconductor device is provided, in which buffer layers having a coefficient of linear expansion of 3×10?6/° C. to 8×10?6/° C. are joined to upper and lower surfaces of a silicon chip through a Pb-free solder having a thickness of not more than 0.05 mm and a melting point of not less than 250° C. The upper surface of the upper buffer layer and the lower surface of the lower buffer layer are respectively joined to a lead and a base through Pb-free solders having a thickness of not less than 0.15 mm and a melting point of not less than 250° C.
    Type: Application
    Filed: November 29, 2005
    Publication date: September 28, 2006
    Inventors: Koji Sasaki, Shinji Hiramitsu, Tadaaki Kariya, Satoshi Matsuyoshi, Ryouichi Kajiwara, Shosaku Ishihara
  • Patent number: 5148049
    Abstract: A driving circuit suitable for driving a capacitive load such as an EL display panel is disclosed, which comprises a first power source terminal; a second power source terminal; an output terminal, with which a capacitive load is connected; a source side thyristor connected between the first power source terminal and the output terminal, and supplying current to the load; a sink side thyristor connected between the second power source terminal and the output terminal and drawing-out current from the load; and a control section connected between the first power source terminal and the second power source terminal and ON-OFF controlling the source side thyristor and the sink side thyristor through a circuit arrangement coupled between the control circuit and the gates of the thyristors.
    Type: Grant
    Filed: September 11, 1989
    Date of Patent: September 15, 1992
    Assignees: Hitachi, Ltd., Hitachi Engineering Ltd.
    Inventors: Mitsuhiko Okutsu, Kenji Abe, Tadaaki Kariya
  • Patent number: 5097160
    Abstract: A method of transmitting a pulse signal composed of a combination of a positive pulse and a negative pulse through a semiconductor switch providing a conduction modulation in the on-state, the positive pulse and negative pulse flowing through the semiconductor switch in the forward and reverse directions, respectively, relative to the semiconductor switch. An offset current is superposed upon the pulse signal so as to make the absolute value of the positive pulse larger than that of the negative pulse.
    Type: Grant
    Filed: March 16, 1990
    Date of Patent: March 17, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Shigeyuki Kawahata, Susumu Murakami, Eisuke Sato, Tadaaki Kariya, Kazunori Morozumi
  • Patent number: 5083180
    Abstract: A lateral-type semiconductor device is provided in which a p-emitter layer and a p-collector layer are formed on the exposed-surface side of an n-base layer. The exposed surfaces of the p-emitter layer and the n-base layer are substantially surrounded by the exposed surface of the p-collector layer. The n-base layer is connected to a base electrode or through a first heavily-doped region extending from under the n-base region to an exposed surface area on the outer-periphery side of the p-collector layer. In an alternative embodiment a second heavily-doped region for connecting the n-base layer and the first heavily-doped region can be provided.
    Type: Grant
    Filed: October 11, 1990
    Date of Patent: January 21, 1992
    Assignees: Hitachi Ltd., Hitachi Haramachi Semiconductor
    Inventors: Masato Miura, Tatsuo Shimura, Tadaaki Kariya, Norihiro Kawauchi, Sinichi Kurita
  • Patent number: 4967100
    Abstract: A capacitive load driving apparatus which has a plurality of first switching elements connected between a plurality of parallel loads and a first power source terminal for switching currents which charge the loads. There is furthermore provided a plurality of bipolar transistors connected between connecting points (of the first switching elements and the loads) and a second power source terminal for discharging charges stored in the loads and a plurality of second switching elements connected between a third power source terminal and bases of the bipolar transistor, respectively, for switching base currents supplied from the third power source terminal to the bipolar transistors.
    Type: Grant
    Filed: December 20, 1988
    Date of Patent: October 30, 1990
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Mitsuhiko Okutsu, Tadaaki Kariya, Kouji Kawamoto, Syuzoh Kaneko, Yasuhiro Mashiko
  • Patent number: 4833587
    Abstract: A fraction of current passing through the P-emitter region and N-base region of a thyristor is by-passed to the base-emitter junction of a PNP transistor. The amount of the base current is dependent on the thyristor current. Thus, as the anode current of the thyristor increases, the base current and hence the collector current of the PNP transistor increases. The collector current by-passed to the PNP transistor is fed, via a switch which is closed during the off-time of the thyistor, to the base-collector path of an NPN transistor whose collector and emitter are respectively connected to the gate and cathode of the thyristor. The turn-on voltage across the collector and emitter of the NPN transistor accordingly becomes lower than the gate-cathode voltage of the thyristor. The base-emitter current of the NPN transistor equals the collector current of the PNP transistor, the collector current being a fraction of the anode current by-passed to the PNP transistor.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: May 23, 1989
    Assignee: Hitachi Ltd. and Hitachi Haramachi Semi-Conductor Ltd.
    Inventors: Shigeru Sugayama, Tadaaki Kariya, Tatsuo Shimura, Sigeo Tomita
  • Patent number: 4740723
    Abstract: A voltage across a resistor of a small value connected in series with the cathode or anode of a thyristor is used as a signal source for overcurrent detection. When an overcurrent is generated, the voltage across the resistor increases in excess of the built-in voltage between the base and emitter of a transistor, thereby turning on the transistor. A transistor to take out a current from the gate of the thyristor is turned on. Thus, the self-turn off operation of the thyristor is executed.
    Type: Grant
    Filed: March 21, 1986
    Date of Patent: April 26, 1988
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semi-Conductor, Ltd.
    Inventors: Shigeru Sugayama, Tatsuo Shimura, Tadaaki Kariya, Sigeo Tomita
  • Patent number: 4733106
    Abstract: A device for driving a capacitive load, comprising a first switching element responsive to an external control signal for selectively conducting a charge current therethrough to the load, a second switching element responsive to the external control signal for conducting a discharge current from the load and a generator for generating from the discharge current a cutoff signal to be applied to the first switching element to ensure turn-off of the latter.
    Type: Grant
    Filed: April 1, 1985
    Date of Patent: March 22, 1988
    Assignees: Hitachi, Ltd., Hitachi Engineering Co.
    Inventors: Mitsuhiko Okutsu, Tatsuo Shimura, Tadaaki Kariya
  • Patent number: 4728825
    Abstract: In a bidirectional linear switch in which two MOS transistors are used with their sources mutually connected, the gates and the substrates of the transistors are also respectively mutually connected and a control signal is applied to the gates. A potential of the polarity such that the substrates are reversely biased to the sources is applied between the substrates and the sources. With this constitution, the linearity of the bidirectional switch is improved.
    Type: Grant
    Filed: May 29, 1986
    Date of Patent: March 1, 1988
    Assignees: Haramachi Semi-Hitachi Ltd., Hitachi Conductor Ltd.
    Inventors: Shigeru Sugayama, Tadaaki Kariya, Tatsuo Shimura, Sigeo Tomita
  • Patent number: 4725770
    Abstract: A reference voltage circuit in which an output reference voltage is stabilized against variations in power source as well as in transistor current amplification factor h.sub.FE.
    Type: Grant
    Filed: February 11, 1987
    Date of Patent: February 16, 1988
    Assignees: Hitachi, Ltd., Hitachi Engineering Co.
    Inventors: Mitsuhiko Okutsu, Tatsuo Shimura, Tadaaki Kariya, Kazuyoshi Masuda
  • Patent number: 4298881
    Abstract: This invention concerns a so-called double-moat uni-surface type semiconductor device in which two concentric moats are provided in one main surface of the substrate and the edges of the two pn-junctions for blocking main circuit voltages applied to the device are exposed in the surfaces of the moats. Semiconductor layers having high impurity concentrations and serving as channel stoppers are formed on the semiconductor layers exposed in the one main surface of the substrate, contiguous to the moats and spaced apart from the pn-junctions, each high impurity concentration layer having the same conductivity type as the semiconductor layer on which it is formed. The moats are filled with surface passivating material.
    Type: Grant
    Filed: April 7, 1980
    Date of Patent: November 3, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Shuroku Sakurada, Yoichi Nakashima, Isao Kojima, Hideyuki Yagi, Tadaaki Kariya, Masayoshi Sugiyama