Patents by Inventor Tadaaki Mimura
Tadaaki Mimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8669555Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: GrantFiled: November 23, 2012Date of Patent: March 11, 2014Assignee: Panasonic CorporationInventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
-
Patent number: 8338829Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: GrantFiled: July 8, 2011Date of Patent: December 25, 2012Assignee: Panasonic CorporationInventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
-
Publication number: 20110266540Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Applicant: Panasonic CorporationInventors: Masao TAKAHASHI, Koji TAKEMURA, Toshihiko SAKASHITA, Tadaaki MIMURA
-
Publication number: 20110233772Abstract: A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line.Type: ApplicationFiled: June 2, 2011Publication date: September 29, 2011Applicant: Panasonic CorporationInventors: Hiroaki FUJIMOTO, Noriyuki Nagai, Tadaaki Mimura
-
Patent number: 7999256Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: GrantFiled: September 11, 2008Date of Patent: August 16, 2011Assignee: Panasonic CorporationInventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
-
Patent number: 7741207Abstract: A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.Type: GrantFiled: November 14, 2007Date of Patent: June 22, 2010Assignee: Panasonic CorporationInventors: Shin Hashimoto, Tadaaki Mimura
-
Publication number: 20090289357Abstract: A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line.Type: ApplicationFiled: February 4, 2009Publication date: November 26, 2009Inventors: Hiroaki FUJIMOTO, Noriyuki NAGAI, Tadaaki MIMURA
-
Publication number: 20090078935Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.Type: ApplicationFiled: September 11, 2008Publication date: March 26, 2009Inventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
-
Publication number: 20080284026Abstract: A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.Type: ApplicationFiled: November 14, 2007Publication date: November 20, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shin Hashimoto, Tadaaki Mimura
-
Patent number: 7391114Abstract: A pad section serving as an electrode for external connection of a semiconductor device includes a first pad metal (61) formed in the top layer, a second pad metal (62) formed under the first pad metal (61) via an interlayer insulating film (71), and vias (63) which penetrate the interlayer insulating film (71) and electrically connect the first pad metal (61) and the second pad metal (62). The first pad metal (61) and the second pad metal (62) have edges displaced from each other so as not to be aligned with each other along the thickness direction of each layer. Thus, it is possible to reduce stress occurring on an edge of the second pad metal (62), thereby reducing damage on the interlayer insulating film (71) and so on.Type: GrantFiled: February 1, 2005Date of Patent: June 24, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadaaki Mimura, Tsuyoshi Hamatani, Atuhito Mizutani, Kenji Ueda
-
Patent number: 7312530Abstract: A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.Type: GrantFiled: September 22, 2004Date of Patent: December 25, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shin Hashimoto, Tadaaki Mimura
-
Publication number: 20070023927Abstract: When an interlayer film (22) is formed to have a large thickness and an electrode pad (11) is partly or wholly led out from an active region (16), an I/O region (15) can be reduced in area. Thus, it is possible to reduce an area of a semiconductor device.Type: ApplicationFiled: July 17, 2006Publication date: February 1, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Noriyuki Nagai, Tsuyoshi Hamatani, Tadaaki Mimura
-
Patent number: 7170189Abstract: Circuits under electrode terminals and a nonconductor layer of the electrode terminals in semiconductor devices are prevented from being damaged during a test, such as a burn-in test, on the semiconductor devices formed on a wafer. Alignment patterns provided on the semiconductor wafer have detector electrode terminals and conductor electrode terminals. A detector electrode terminal surrounds a conductor electrode terminal separated by a gap from the detector electrode terminals and a portion of the surrounding detector electrode terminal is open.Type: GrantFiled: October 7, 2005Date of Patent: January 30, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masao Takahashi, Yoshirou Nakata, Tadaaki Mimura, Toshihiko Sakashita, Toshiyuki Fukuda
-
Publication number: 20060103408Abstract: Circuits under electrode terminals and a nonconductor layer of the electrode terminals in semiconductor devices are prevented from being damaged during a test, such as a burn-in test, on the semiconductor devices formed on a wafer. Alignment patterns provided on the semiconductor wafer have detector electrode terminals and conductor electrode terminals. A detector electrode terminal surrounds a conductor electrode terminal separated by a gap from the detector electrode terminals and a portion of the surrounding detector electrode terminal is open.Type: ApplicationFiled: October 7, 2005Publication date: May 18, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masao Takahashi, Yoshirou Nakata, Tadaaki Mimura, Toshihiko Sakashita, Toshiyuki Fukuda
-
Publication number: 20050173801Abstract: A pad section serving as an electrode for external connection of a semiconductor device includes a first pad metal (61) formed in the top layer, a second pad metal (62) formed under the first pad metal (61) via an interlayer insulating film (71), and vias (63) which penetrate the interlayer insulating film (71) and electrically connect the first pad metal (61) and the second pad metal (62). The first pad metal (61) and the second pad metal (62) have edges displaced from each other so as not to be aligned with each other along the thickness direction of each layer. Thus, it is possible to reduce stress occurring on an edge of the second pad metal (62), thereby reducing damage on the interlayer insulating film (71) and so on.Type: ApplicationFiled: February 1, 2005Publication date: August 11, 2005Applicant: Matsushita Elec. Ind. Co. Ltd.Inventors: Tadaaki Mimura, Tsuyoshi Hamatani, Atuhito Mizutani, Kenji Ueda
-
Publication number: 20050067707Abstract: A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.Type: ApplicationFiled: September 22, 2004Publication date: March 31, 2005Inventors: Shin Hashimoto, Tadaaki Mimura
-
Patent number: 5821625Abstract: The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: April 23, 1996Date of Patent: October 13, 1998Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corp.Inventors: Takayuki Yoshida, Takashi Otsuka, Hiroaki Fujimoto, Tadaaki Mimura, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga
-
Patent number: 5805865Abstract: A microcomputer chip is formed with a CPU core, a peripheral circuit, a built-in ROM, and a built-in RAM. An emulation functional chip is formed with an emulation control circuit for controlling the whole process of emulation. First electrode pads formed on the functional surface of the microcomputer chip are electrically interconnected to second electrode pads formed on the functional surface of the emulation functional chip with connecting bumps interposed therebetween. The microcomputer chip and the emulation functional chip are modularized using an insulating resin with the first electrode pads being connected to the second electrode pads.Type: GrantFiled: September 26, 1996Date of Patent: September 8, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadaaki Mimura, Takayuki Yoshida, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga, Hiroaki Fujimoto
-
Patent number: 5767009Abstract: The present invention reduces crosstalk noise, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip (1) having a first electrode pad (2) and a first wiring layer (9), and a second semiconductor chip (5) having a second electrode pad (6) and a second wiring layer (10). A bump (4) is provided for electrically coupling the first electrode pad (2) and the second electrode pad (6). An insulation layer 8 is disposed between confronting surfaces of the first semiconductor chip (1) and the second semiconductor chip (5). An electro-conductive layer (7) is disposed between the confronting surfaces of the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: February 10, 1997Date of Patent: June 16, 1998Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corp.Inventors: Takayuki Yoshida, Takashi Otsuka, Hiroaki Fujimoto, Tadaaki Mimura, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga