Abstract: To provide a checking method that utilizes a test bench for a circuit model, which will serve as a fundamental for equivalence checking of a circuit to be newly developed for the fundamental circuit model. In order to check the equivalence of a model to be verified using a sample model a circuit of which has been described in a predetermined language and a test vector generation model for the sample model, a process for writing an output from the sample model test vector generation model into an input FIFO group for each signal of the sample model with the same timing as that of the sample model while the sample model is inputting/outputting a signal from/to the sample model test vector generation model with cycle accuracy and a process for reading data from the input FIFO group with the same operation timing as that of the model to be verified and outputting the data to the model to be verified are carried out.

Abstract: To provide a checking method that utilizes a test bench for a circuit model, which will serve as a fundamental for equivalence checking of a circuit to be newly developed for the fundamental circuit model. In order to check the equivalence of a model to be verified using a sample model a circuit of which has been described in a predetermined language and a test vector generation model for the sample model, a process for writing an output from the sample model test vector generation model into an input FIFO group for each signal of the sample model with the same timing as that of the sample model while the sample model is inputting/outputting a signal from/to the sample model test vector generation model with cycle accuracy and a process for reading data from the input FIFO group with the same operation timing as that of the model to be verified and outputting the data to the model to be verified are carried out.

Abstract: A compiler in which pseudo C descriptions (1) that are capable of describing parallel operations at a statement level and at a cycle precision by clock boundaries and register assignment statements are input, the register assignment statements are identified (S2), so as to generate executable C descriptions (3), to extract state machines having undergone reductions in the numbers of states, and to decide whether or not a loop to be executed in the 0th cycle is existent (S5), and if the loop is nonexistent, circuit descriptions (4) that are capable of being logically synthesized are generated. Thus, the pseudo C descriptions in which the clock boundaries are explicitly inserted into the C descriptions are input, and the pseudo C descriptions which permit the register assignment statements to be described in parallel at the statement level are input, so that a pipeline operation attended with a stall operation can be represented.

Abstract: Program descriptions (1) which define a plurality of devices by employing a program language capable of describing parallel operations are input, the input program descriptions are converted into an intermediate expression (S2), parameters which satisfy a real-time restriction are generated for the intermediate expression (S3), and circuit descriptions which are based on a hardware description language are synthesized on the basis of the generated parameters (S4). The intermediate expression is a concurrent control flow flag, a temporal automaton having a concurrent parameter, or the like. Parametric model checking is performed for the parameter generation. The program descriptions define the devices by using a “run” method, and define the clock synchronizations of the devices by using barrier synchronizations. Thus, a bus system meeting the real-time restriction can be designed.

Abstract: A compiler in which pseudo C descriptions (1) that are capable of describing parallel operations at a statement level and at a cycle precision by clock boundaries and register assignment statements are input, the register assignment statements are identified (S2), so as to generate executable C descriptions (3), to extract state machines having undergone reductions in the numbers of states, and to decide whether or not a loop to be executed in the 0th cycle is existent (S5), and if the loop is nonexistent, circuit descriptions (4) that are capable of being logically synthesized are generated. Thus, the pseudo C descriptions in which the clock boundaries are explicitly inserted into the C descriptions are input, and the pseudo C descriptions which permit the register assignment statements to be described in parallel at the statement level are input, so that a pipeline operation attended with a stall operation can be represented.

Abstract: The timing for a mixed circuit of a synchronous circuit and an asynchronous circuit classifies the synchronous circuit into a cyclic circuit and an acyclic circuit, and the asynchronous circuit into a cyclic circuit and an acyclic circuit. The cyclic circuit of the synchronous circuit and the cyclic circuit of the asynchronous circuit thus classified are subjected to a static timing analysis, whereas the acyclic circuit of the synchronous circuit and the acyclic circuit of the asynchronous circuit thus classified are subjected to a dynamic timing analysis. As a result, the timing analysis can be made considering a hazard of the synchronous circuit, and the circuit to be operated in response to a signal, as can be virtually deemed as a clock, is subjected to the static timing analysis so that the analyzing operation can be made efficient.

Abstract: The optimization algorithm candidate of a plurality of circuit blocks given with the logic circuit description based on the hardware description language is determined considering the Hamming distance of circuit block (S1 to S3). The common circuit blocks of the optimization algorithm candidate determined in the first process are then grouped considering the coupling degree among circuit blocks (S4 to S6). Result of grouping is the result for the circuit blocks having apparent characteristic in the algorithm candidate and coupling degree and the circuit blocks having uncertain characteristics are also left. In view of optimizing the grouping for the circuit blocks having uncertain characteristics, the grouping of a plurality of circuit blocks is optimized with the hereditary algorithm by reflecting the result of grouping on the initial condition.

Abstract: The optimization algorithm candidate of a plurality of circuit blocks given with the logic circuit description based on the hardware description language is determined considering the Hamming distance of circuit block (S1 to S3). The common circuit blocks of the optimization algorithm candidate determined in the first process are then grouped considering the coupling degree among circuit blocks (S4 to S6). Result of grouping is the result for the circuit blocks having apparent characteristic in the algorithm candidate and coupling degree and the circuit blocks having uncertain characteristics are also left. In view of optimizing the grouping for the circuit blocks having uncertain characteristics, the grouping of a plurality of circuit blocks is optimized with the hereditary algorithm by reflecting the result of grouping on the initial condition.