Patents by Inventor Tadaaki YOSHIMURA

Tadaaki YOSHIMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses and methods for coupling semiconductor devices of a memory module in a memory system
    Patent number: 9524756
    Abstract: A system includes memory chips mounted on a memory module each having an alert terminal that notifies that the memory chip has detected a predetermined error. The memory module has a first transmission line connected to alert terminals of memory chips, output terminal being connected to one end of the first transmission line, and a first termination resistor having an end connected to another end of the first transmission line. The system further includes a second transmission line having an end connected to the alert terminal and another end connected to a controller and a third transmission line having an end connected to a first input terminal on the memory module and a second end line and a second end having a voltage different from a voltage of another end of the first termination resistor.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: December 20, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Yoji Nishio, Tadaaki Yoshimura, Koji Matsuo
  • Semiconductor module includes semiconductor chip initialized by reset signal
    Patent number: 8953406
    Abstract: Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 10, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Yoji Nishio, Takao Hirayama, Susumu Hatano, Haruki Nagahashi, Masashi Kawamura, Tadaaki Yoshimura
  • SEMICONDUCTOR DEVICES
    Publication number: 20140233335
    Abstract: A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100. Memory module 100 has a first transmission line connected to an alert terminal of each of the plurality of memory chips, output terminal 101 being connected to one end of the first transmission line, and a first termination resistor being connected to another end of the first transmission line.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 21, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Yoji NISHIO, Tadaaki Yoshimura, Koji Matsuo
  • Method for extracting IBIS simulation model
    Patent number: 8738347
    Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: May 27, 2014
    Inventors: Tadaaki Yoshimura, Yoji Nishio, Sadahiro Nonoyama, Koji Matsuo, Shinji Itano, Yoshiyuki Yagami
  • SEMICONDUCTOR MODULE INCLUDES SEMICONDUCTOR CHIP INITIALIZED BY RESET SIGNAL
    Publication number: 20120268173
    Abstract: Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.
    Type: Application
    Filed: April 25, 2012
    Publication date: October 25, 2012
    Inventors: Yoji NISHIO, Takao HIRAYAMA, Susumu HATANO, Haruki NAGAHASHI, Masashi KAWAMURA, Tadaaki YOSHIMURA
  • METHOD FOR EXTRACTING IBIS SIMULATION MODEL
    Publication number: 20120191437
    Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 26, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tadaaki YOSHIMURA, Yoji NISHIO, Sadahiro NONOYAMA, Koji MATSUO, Shinji ITANO, Yoshiyuki YAGAMI