Patents by Inventor Tadaaki Yuba

Tadaaki Yuba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230259485
    Abstract: The present disclosure relates to a communication apparatus, a communication method, and a program that enable more reliable communication. An I3C master transmits a parameter having been changed to an I3C slave during communication in Sync Mode with the I3C slave, and gives an instruction on a timing at which the parameter having been changed is reflected in the I3C slave by transmitting a predetermined command. The I3C slave holds the parameter having been changed, the parameter being received during communication in Sync Mode with the I3C master, and determines to reflect the parameter having been changed at a timing at which the predetermined command is transmitted from the I3C master. The present technology can be applied to, for example, an I3C bus.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 17, 2023
    Inventors: KOHEI KAWANISHI, TADAAKI YUBA
  • Publication number: 20230222074
    Abstract: A transmission device according to an aspect of the present disclosure communicates with a reception device via a control data bus. The transmission device includes a generation unit that generates an interrupt request, and a transmission section that transmits data to the reception device via the control data bus. The interrupt request includes at least an identification bit to identify a type of transmission data, an information bit for the transmission data, and the transmission data.
    Type: Application
    Filed: February 5, 2021
    Publication date: July 13, 2023
    Inventors: HIROO TAKAHASHI, MAKOTO NARIYA, TADAAKI YUBA
  • Patent number: 11435928
    Abstract: A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 6, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Jun Ueshima, Takahiro Okada, Tadaaki Yuba, Ken Matsumoto, Shinichi Tsuchida
  • Publication number: 20220276980
    Abstract: A transmission device communicates with a reception device via a control data bus in a communication standard of I3C. The transmission device includes a transfer mode switching section and a data transmission section. The transfer mode switching section switches a transfer mode of the control data bus from a first transfer mode having a first transfer rate to a second transfer mode having a second transfer rate faster than the first transfer rate by transmitting a switching command instructing to switch to the second transfer mode after issuance of an IBI request using a function of the I3C in the first transfer mode. The data transmission section transmits data to the reception device via the control data bus in the second transfer mode.
    Type: Application
    Filed: October 1, 2020
    Publication date: September 1, 2022
    Inventors: Yuichi Mizutani, Tadaaki Yuba
  • Patent number: 11080167
    Abstract: A debug work is performed with respect to states after execution of a plurality of commands which is collectively issued from a processor to an arithmetic processing apparatus. A command register group holds commands issued from the processor in respective registers with a command chain including a plurality of commands as a unit. A command processing section processes the commands supplied from the command register group. A state machine manages processing states of the commands in the command processing section. A control section previously sets a condition under which stop is to be performed in the command chain as a stop condition and causes to stop the processing in the command processing section on the basis of the previously set stop condition and the processing states managed in the state machine.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 3, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takahiro Okada, Tadaaki Yuba, Jun Ueshima, Shinichi Tsuchida, Ken Matsumoto
  • Publication number: 20190361796
    Abstract: A debug work is performed with respect to states after execution of a plurality of commands which is collectively issued from a processor to an arithmetic processing apparatus. A command register group holds commands issued from the processor in respective registers with a command chain including a plurality of commands as a unit. A command processing section processes the commands supplied from the command register group. A state machine manages processing states of the commands in the command processing section. A control section previously sets a condition under which stop is to be performed in the command chain as a stop condition and causes to stop the processing in the command processing section on the basis of the previously set stop condition and the processing states managed in the state machine.
    Type: Application
    Filed: December 14, 2017
    Publication date: November 28, 2019
    Inventors: TAKAHIRO OKADA, TADAAKI YUBA, JUN UESHIMA, SHINICHI TSUCHIDA, KEN MATSUMOTO
  • Publication number: 20190347030
    Abstract: A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.
    Type: Application
    Filed: October 13, 2017
    Publication date: November 14, 2019
    Inventors: Jun Ueshima, Takahiro Okada, Tadaaki Yuba, Ken Matsumoto, Shinichi Tsuchida
  • Patent number: 9203674
    Abstract: The present technique relates to a receiving device, a receiving method, and a program that are designed to improve reception performance. A receiving device according to one aspect of the present technique includes: a gain control unit that adjusts the power of a signal including a first pilot signal transmitted as signals having a high correlation in terms of polar direction via different transmission channels, and a second pilot signal transmitted as signals having a low correlation in terms of polar direction via the different transmission channels; and a control unit that controls the followability of the gain at the gain control unit in accordance with a data transmission method. The present technique can be applied to a receiver that receives data transmitted by MISO (Multi Input, Single Output) compliant with the DVB-T2 standards.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: December 1, 2015
    Assignee: SONY CORPORATION
    Inventors: Kenichi Kobayashi, Tadaaki Yuba, Hiroyuki Kamata
  • Publication number: 20130329839
    Abstract: The present technique relates to a receiving device, a receiving method, and a program that are designed to improve reception performance. A receiving device according to one aspect of the present technique includes: a gain control unit that adjusts the power of a signal including a first pilot signal transmitted as signals having a high correlation in terms of polar direction via different transmission channels, and a second pilot signal transmitted as signals having a low correlation in terms of polar direction via the different transmission channels; and a control unit that controls the followability of the gain at the gain control unit in accordance with a data transmission method. The present technique can be applied to a receiver that receives data transmitted by MISO (Multi Input, Single Output) compliant with the DVB-T2 standards.
    Type: Application
    Filed: March 1, 2012
    Publication date: December 12, 2013
    Applicant: SONY CORPORATION
    Inventors: Kenichi Kobayashi, Tadaaki Yuba, Hiroyuki Kamata
  • Patent number: 8488695
    Abstract: A receiving apparatus for receiving an orthogonal frequency division multiplexing (OFDM) signal including a frame having one frame length of a plurality of patterns. The apparatus comprises an acquiring section to acquire information regarding a preamble signal from an OFDM signal from a transmitting apparatus; a frame determining section to determine whether the one frame length is short in the frame based on the information regarding the acquired preamble signal; and a time interpolating section to obtain transmission path characteristics by comparing a pilot contained in the preamble signal with a known pilot corresponding to the pilot in a phase of transmission, when the frame determining section determines that the one frame length is short in the frame, and to interpolate a data portion in a time direction based on transmission path characteristics.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: July 16, 2013
    Assignee: Sony Corporation
    Inventors: Takashi Yokokawa, Tadaaki Yuba, Hidetoshi Kawauchi, Hitoshi Sakai, Yuken Goto, Suguru Houchi
  • Patent number: 8358722
    Abstract: Disclosed herein is a signal processing apparatus including a processing block configured to perform a carrier shift amount detection process for detecting a carrier shift amount constituting a carrier error used for demodulating an orthogonal frequency division multiplexing signal known as the OFDM signal; and a correction block configured to correct the OFDM signal in accordance with the carrier shift amount. The OFDM signal includes a first preamble signal including subcarriers, and a second preamble signal including subcarriers of which the spacing is narrower than the spacing of the subcarriers included in the first preamble signal. The second preamble signal includes pilot signals which are known signals located at intervals of a predetermined number of subcarriers. The processing block detects the carrier shift amount using a correlation of the subcarriers included in one such second preamble signal.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: January 22, 2013
    Assignee: Sony Corporation
    Inventors: Tadaaki Yuba, Takuya Okamoto, Yuken Goto, Kenichi Kobayashi
  • Patent number: 8045658
    Abstract: A reception apparatus includes: an extraction section; a transmission line characteristic estimation section; an estimation section; a frequency shift amount production section; a control section; an addition section; a first frequency shifting section; a second frequency shifting section; an interpolation section; a compensation section; a detection section; and an operation section.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: October 25, 2011
    Assignee: Sony Corporation
    Inventors: Hidetoshi Kawauchi, Tadaaki Yuba, Tamotsu Ikeda, Koji Naniwada, Kazuhiro Shimizu, Lachlan Bruce Michael
  • Patent number: 8045945
    Abstract: A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: October 25, 2011
    Assignee: Sony Corporation
    Inventors: Hidetoshi Kawauchi, Tadaaki Yuba, Toshiyuki Miyauchi, Takashi Yokokawa, Takuya Okamoto, Tamotsu Ikeda, Koji Naniwada, Kazuhiro Shimizu, Lachlan Bruce Michael
  • Publication number: 20110142176
    Abstract: Disclosed herein is a receiving apparatus for receiving an orthogonal frequency division multiplexing signal, namely, OFDM signal having a frame having one frame length of a plurality of patterns, including: an acquiring section configured to acquire information on a preamble signal from the OFDM signal transmitted from a transmitting apparatus in accordance with an OFDM system; a frame determining section configured to determine whether or not the one frame length is short in the frame based on the information on the preamble signal acquired from the acquiring section; and a time interpolating section configured to obtain transmission path characteristics by comparing a pilot contained in the preamble signal and a known pilot corresponding to the pilot in a phase of transmission with each other when the frame determining section determines that the one frame length is short in the frame, and interpolate a data portion in a time direction based on the transmission path characteristics thus obtained.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 16, 2011
    Applicant: Sony Corporation
    Inventors: Takashi YOKOKAWA, Tadaaki Yuba, Hidetoshi Kawauchi, Hitoshi Sakai, Yuken Goto, Suguru Houchi
  • Publication number: 20110013729
    Abstract: Disclosed herein is a signal processing apparatus including a processing block configured to perform a carrier shift amount detection process for detecting a carrier shift amount constituting a carrier error used for demodulating an orthogonal frequency division multiplexing signal known as the OFDM signal; and a correction block configured to correct the OFDM signal in accordance with the carrier shift amount. The OFDM signal includes a first preamble signal including subcarriers, and a second preamble signal including subcarriers of which the spacing is narrower than the spacing of the subcarriers included in the first preamble signal. The second preamble signal includes pilot signals which are known signals located at intervals of a predetermined number of subcarriers. The processing block detects the carrier shift amount using a correlation of the subcarriers included in one such second preamble signal.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 20, 2011
    Inventors: Tadaaki YUBA, Takuya OKAMOTO, Yuken GOTO, Kenichi KOBAYASHI
  • Publication number: 20090221254
    Abstract: A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.
    Type: Application
    Filed: February 26, 2009
    Publication date: September 3, 2009
    Inventors: Hidetoshi Kawauchi, Tadaaki Yuba, Toshiyuki Miyauchi, Takashi Yokokawa, Takuya Okamoto, Tamotsu Ikeda, Koji Naniwada, Kazuhiro Shimizu, Lachlan Bruce Michael
  • Publication number: 20090110127
    Abstract: A reception apparatus includes: an extraction section; a transmission line characteristic estimation section; an estimation section; a frequency shift amount production section; a control section; an addition section; a first frequency shifting section; a second frequency shifting section; an interpolation section; a compensation section; a detection section; and an operation section.
    Type: Application
    Filed: October 28, 2008
    Publication date: April 30, 2009
    Inventors: Hidetoshi KAWAUCHI, Tadaaki YUBA, Tamotsu IKEDA, Koji NANIWADA, Kazuhiro SHIMIZU, Lachlan Bruce MICHAEL