Patents by Inventor Tadaharu Tsuyuki

Tadaharu Tsuyuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4038680
    Abstract: A semiconductor integrated circuit device having a construction of complementary PNP-NPN semiconductor devices in a monolithic integrated form. First and second N type epitaxial layers are formed on a common P type semiconductor substrate. A base region of the PNP transistor is produced by the diffusion of an impurity into the second epitaxial layer. The NPN transistor is formed as low emitter concentration type transistor and a part of the second epitaxial layer serves as the emitter region of the NPN transistor.
    Type: Grant
    Filed: February 3, 1976
    Date of Patent: July 26, 1977
    Assignee: Sony Corporation
    Inventors: Hajime Yagi, Tadaharu Tsuyuki
  • Patent number: 4032956
    Abstract: A transistor circuit is disclosed in which a region with opposite conductivity type to that of an emitter region or a MOS type structure is disposed adjacent to the emitter region within the diffusion length from an emitter-base junction. A gain control circuit is constructed by varying the emitter-grounded current amplification factor h.sub.FE of a transistor.
    Type: Grant
    Filed: April 17, 1975
    Date of Patent: June 28, 1977
    Assignee: Sony Corporation
    Inventors: Hajime Yagi, Tadaharu Tsuyuki
  • Patent number: 4032957
    Abstract: A semiconductor device having a high emitter-grounded current gain which includes an emitter region with the minority carrier diffusion length greater than its width and an additional region adjacent to the emitter region with the minority carrier diffusion length of this additional region greater than its width. The surface recombination velocity of the additional region is small. The minority carrier current injected from the additional region into the emitter balances that injected from the base into the emitter.
    Type: Grant
    Filed: October 7, 1975
    Date of Patent: June 28, 1977
    Assignee: Sony Corporation
    Inventors: Hajime Yagi, Tadaharu Tsuyuki
  • Patent number: 4032958
    Abstract: An NPN-type bipolar transistor is disclosed which has an additional P-type conductivity in its emitter region. The current-amplification factor h.sub.FE of the transistor is high when the additional region is electrically floated, while the amplification factor h.sub.FE is lower when the additional region is supplied with an emitter potential. The device is so designed and constructed that the transistor factor h.sub.FE can be variably controlled over a wide range. The transistor operates as an h.sub.FE controlled transistor. A thyristor is also disclosed which includes a cathode, a gate, and an electrically floated base electrode and which has an additional region formed in the cathode. This additional region is used as a second gate in addition to an ordinary gate, and either of the gates may be used for ON- and OFF- operations.
    Type: Grant
    Filed: October 15, 1975
    Date of Patent: June 28, 1977
    Assignee: Sony Corporation
    Inventors: Hajime Yagi, Tadaharu Tsuyuki
  • Patent number: 4027324
    Abstract: This invention relates to a bidirectional transistor, and particularly to a transistor having two low impurity concentration regions on either side of a base region which act as the emitter or collector regions with a minority carrier diffusion length L substantially greater than the width of such emitter and collector regions when operating in either direction. High impurity concentration regions interface with the low impurity concentration regions to provide a built-in-field which is larger than kT/(qL) and which make the drift current produced by the built-in-field substantially balance the minority carrier diffusion current injected from the base region. The built-in-field is preferably larger than 10.sup.3 V/cm, and the potential barrier across is preferably larger than 0.1 eV. Two of the high impurity concentration regions provide first and second L-H junctions. A third L-H junction surrounds one of the low impurity concentration regions.
    Type: Grant
    Filed: January 21, 1976
    Date of Patent: May 31, 1977
    Assignee: Sony Corporation
    Inventors: Hajime Yagi, Tadaharu Tsuyuki
  • Patent number: 4007474
    Abstract: A semiconductor device having a high current amplification gain which includes a low impurity concentration in the emitter region of the device, an injected minority carrier diffusion length L greater than the width of the emitter, and a high impurity concentration region of the same type as the emitter overlying at least a portion of said emitter region which provides a built-in-field where there is a drift current of minority carriers back toward the base region. The built-in field is larger than kT(qL) so that the drift current adjacent the built-in-field substantially cancels the minority carrier diffusion current injected from the base region.
    Type: Grant
    Filed: March 25, 1975
    Date of Patent: February 8, 1977
    Assignee: Sony Corporation
    Inventors: Hajime Yagi, Tadaharu Tsuyuki
  • Patent number: 3979766
    Abstract: A semiconductor device is disclosed which comprises a first region of a first conductivity type, a second region of a second conductivity type and adjacent to said first region, a third region of the first conductivity type and adjacent to fifth regions of the second conductivity type and adjacent to said third region, respectively, and in which said second region is interposed between said first and third regions to isolate them from each other; said third region is interposed between said second, fourth and fifth regions to isolate them from one another; and said first and fifth regions are electrically coupled with each other.
    Type: Grant
    Filed: June 19, 1974
    Date of Patent: September 7, 1976
    Assignee: Sony Corporation
    Inventor: Tadaharu Tsuyuki
  • Patent number: 3969747
    Abstract: An integrated circuit including an NPN transistor and a compound PNP transistor. The PNP transistor is of the form of a conventional vertical NPN transistor, in common base configuration, supplying base current to a lateral PNP transistor. The emitter of the vertical NPN is disposed in the emitter of the lateral PNP; the base and collector of the vertical NPN are the emitter and base regions, respectively, of the lateral PNP. The separate NPN transistor may be of conventional configuration, or may also be compound, with a lateral PNP supplying base current to an inverse vertical NPN. All conductivity types may be reversed from those listed, also.
    Type: Grant
    Filed: June 10, 1974
    Date of Patent: July 13, 1976
    Assignee: Sony Corporation
    Inventors: Tadaharu Tsuyuki, Hajime Yagi, Toshiro Kobayashi
  • Patent number: 3968511
    Abstract: A bipolar transistor has an emitter, a base, a collector and additional region which is electrically connected to the base region. The additional region is formed parallel to an emitter-base junction to inject minority carriers into the emitter and has a plurality of windows therein where a plurality of ohmic contacts for the emitter are located.
    Type: Grant
    Filed: November 11, 1974
    Date of Patent: July 6, 1976
    Assignee: Sony Corporation
    Inventors: Hajime Yagi, Tadaharu Tsuyuki, Kotaro Koma, Yoshihiro Miyazawa