Abstract: An integrated circuit is fabricated on a semiconductor substrate and comprises an n channel type field effect transistor, a p channel type field effect transistor and an interconnection coupled between the drain regions of the two field effect transistors, and each of the gate electrodes and the interconnection is provided with a polycrystalline silicon and a refractory metal silicide deposited over the polycrystalline silicon, wherein side spacers are eliminated from the gate electrodes and the interconnection, because no short circuiting takes place between the gate electrodes and the source and drain regions by virtue of the deposition of the refractory metal silicide.

Abstract: An electrode using Ti or Zr having a highly reactive property but insuring a good and stable electric contact with a silicon semiconductor device surrounded by an oxygen atom-containing insulating film is realized with simplified and reduced manufacturing steps at a reduced cost by first revealing a selective surface region of the silicon semiconductor through a window, and then laminating thereon including the selective surface region a first metal layer of Ti or Zr and then a second metal layer of Mo or W to cover and protect the first metal layer from oxidation, and then etching away the laminated layers leaving that portion corresponding to the selective surface region of the device, and thereafter heating the assembly to form a silicide of the first metal with silicon of the underlying semiconductor. The upper metal layer is covered with a protective insulating layer to avoid oxidation of the upper metal layer.

Abstract: A semiconductor integrated circuit comprising a plurality of vertical static induction transistors (SITs) of normally-off type formed in a common semiconductor substrate in such a manner that the lateral dimension of the channel region of the SITs employed to form a hardware circuit region such as a logic circuit is designed greater than of the SITs which are employed to form a peripheral circuit region. Thus, it is possible to provide a semiconductor integrated circuit which concurrently satisfies a plurality of differently functioning semiconductor circuit requirements to exhibit different electric characteristics as represented by a high-speed operation and a high breakdown voltage.

Abstract: A complementary MOS type integrated circuit is produced by a method which comprises the steps of: disposing a first mask material layer on the surface of a semiconductor substrate, the first mask material layer having a first impurity introducing region corresponding to a desired well forming pattern; forming a well region by selectively doping an impurity into the surface of the substrate through the first impurity introducing region; forming a second mask material layer in such a manner as to cover both the first impurity introducing region and the first mask material layer; disposing first and second mask layers on the second mask material layer, the first and second mask layers respectively corresponding to a first active region pattern within the well region and a second active region pattern outside the well region, thereby defining a second impurity introducing region corresponding to a desired parasitic channel stopper pattern between the stack portion of the first and second mask material layers and

Abstract: A method of manufacturing a semiconductor device manufactures a semiconductor device provided with plural kinds of Schottky barrier diodes having different forward voltages on one substrate. The method includes (a) a step of forming at least one Schottky barrier diode of a first kind, and (b) a step of forming at least one Schottky barrier diode of a second kind. The step (a) is performed by placing a first metal layer at a first surface part of a silicon substrate, and then by silicifying the first metal layer. The step (b) is performed by plating, at a second surface part of the silicon substrate which is different from the first surface part of the silicon substrate, a second metal layer which consists of a metal different from the metal consisting of the first metal layer and then by silicifying the second metal layer.

Abstract: A method of making a semiconductor integrated circuit on a semiconductor substrate containing thereon an SIT and an IG(MOS) FET or an SIT and C-MOS FETs, comprises a series of steps of making these functional semiconductor devices many of which steps are rendered to be common to the SIT and the FET. The gate region of said IG(MOS) FET is formed as a semiconductor gate layer which typically is made of polycrystalline silicon, and an active semiconductor area of said IG(MOS) FET is formed by using this semiconductor gate layer as the mask therefor.

Abstract: A method of manufacturing an SIT or SITL device, comprising simultaneous formation of a gate doping aperture and contact apertures for a source and a drain. Firstly, a gate region is doped through the doping aperture with the contact apertures being covered by a mask. Then, a source region is doped so as to be in self-alignment relation relative to the gate region and a source contact portion is doped so as to be in self-alignment relation relative to the source region and the gate region, whereby the mask alignments are eliminated and packing density is enhanced.

Abstract: In a semiconductor device of the type arranged so that the minority carriers are injected into a lightly-doped n type semiconductor layer from a heavily-doped p type semiconductor layer provided in the n type layer, that portion of the p type layer excluding a certain portion is separated from the n type layer by a separator layer to cause the p type layer to contact the n type layer only at the certain portion, whereby the carrier injection is restricted to occur within a limited region of the n type layer contacting the certain portion of the p type layer. The separator and the p type layer are formed, by relying on a self-alignment technique using a double-mask layer, as diffused regions partially overlapping each other with a good relative alignment in the n type layer.

Abstract: An integrated semiconductor device including at least one first vertical-type junction field effect transistor (vertical JFET) having a triode-like unsaturated voltage-current characteristic and at least one second vertical JFET having a bipolar-transistor-like saturated voltage-current characteristic, both being integrally formed in a semiconductor body. Both the first and second vertical JFET are much similar in general arrangement to each other, thus allowing simultaneous forming thereof by the same manufacturing process, without sacrificing the good characteristics of these two types of transistors.

Abstract: In an integrated semiconductor device of the IIL type which includes a switching transistor and an injector transistor for supplying carriers to drive the switching transistor, the switching transistor is a static induction transistor which comprises: cylindrical current channels for providing current paths between a source and drains; a control gate surrounding the outer boundaries of the channels to form pn junctions therebetween and being injected with carriers from the injector transistor to control the current flow in the channels; and floating gates disposed inside the respective channels to form pn junctions therebetween. The floating gates are electrically floating and have a potential affected by the potential of the control gate to contribute to the channel conduction controlling action together with the control gate.